scispace - formally typeset
Search or ask a question

Showing papers by "Tsunenobu Kimoto published in 2002"


Journal ArticleDOI
TL;DR: In this paper, the parallel conductance as a function of frequency was measured at room temperature and high-frequency capacitance (C)voltage (V) curves were measured both at room-temperature and 100 K.
Abstract: Shallow interface states at SiO2/4H-SiC were examined on (1120) and (0001) faces using metal–oxide–semiconductor (MOS) capacitors. The MOS capacitors were fabricated by wet oxidation on both faces to investigate the difference in the energy distribution of interface state density. The parallel conductance as a function of frequency was measured at room temperature, and high-frequency capacitance (C)–voltage (V) curves were measured both at room temperature and 100 K. By the conductance method, the interface state density on (1120) was revealed smaller than on (0001) at shallow energies, while at deeper energies the relation changes to opposite situation. High-frequency C–V curves at 100 K show a large positive flatband voltage shift and a large injection-type hysteresis on (0001) samples, while those were small on (1120), indicating another evidence of smaller interface state density near the conduction band edge on (1120).

61 citations


Journal ArticleDOI
TL;DR: In this article, the p-type 6H-SiC epilayers were fabricated using horizontal cold-wall chemical vapor deposition (CVD) with nitrogen and aluminum doping, respectively.
Abstract: The p-i-n diodes were fabricated using 31 /spl mu/m thick n/sup -/- and p-type 6H-SiC epilayers grown by horizontal cold-wall chemical vapor deposition (CVD) with nitrogen and aluminum doping, respectively. The diode exhibited a very high breakdown voltage of 4.2 kV with a low on-resistance of 4.6 m/spl Omega/cm/sup 2/. This on-resistance is lower (by a factor of five) than that of a Si p-i-n diode with a similar breakdown voltage. The leakage current density was substantially lower even at high temperatures. The fabricated SiC p-i-n diode showed fast switching with a turn-off time of 0.18 /spl mu/s at 300 K. The carrier lifetime was estimated to be 0.64 /spl mu/s at 300 K, and more than 5.20 /spl mu/s at 500 K. Various characteristics of SiC p-i-n diodes which have an advantage of lower power dissipation owing to conductivity modulation were investigated.

48 citations



Journal ArticleDOI
TL;DR: In this paper, high-dose ion implantation of phosphorus into 4H-SiC has been investigated, achieving a sheet resistance of 80 Ω/□ after annealing at 1700°C.
Abstract: High-dose ion implantation of phosphorus into 4H–SiC has been investigated. Phosphorus ion implantation with a 1×1016 cm−2 dose at 800 °C into 4H–SiC (0001) has resulted in a sheet resistance of 80 Ω/□ after annealing at 1700 °C. A similar sheet resistance of 110 Ω/□ was achieved even by room-temperature implantation when 4H–SiC (1120) was employed, owing to excellent recrystallization of this face revealed by Rutherford backscattering channeling spectroscopy. The sheet resistance could be further reduced down to 27 Ω/□ by 800 °C implantation into 4H–SiC (1120) followed by annealing at 1700 °C. 4H–SiC (1120) showed a very flat surface after annealing.

41 citations


Journal ArticleDOI
TL;DR: In this article, the authors measured the breakdown fields along the 1120 and 0338 directions in 4H-SiC with epitaxial p+n diodes with mesa structures.
Abstract: The breakdown fields along the 〈1120〉 and 〈0338〉 directions in 4H–SiC have been measured. For the measurements, epitaxial p+n diodes with mesa structures were fabricated on the (1120) and (0338) faces, and they showed good rectification properties and avalanche breakdown. The breakdown fields along these directions calculated from the breakdown voltage were found to be about three quarters of that along the 〈0001〉 direction in 4H–SiC. The cause of the anisotropy in breakdown field is discussed.

40 citations


Journal ArticleDOI
TL;DR: In this paper, the interface properties of SiO2/4H-SiC(0338) were characterized using n-type metaloxide-semiconductor structures fabricated by wet oxidation.
Abstract: The interface properties of SiO2/4H-SiC(0338) were characterized using n-type metaloxide-semiconductor structures fabricated by wet oxidation. The interface states near the conduction band edge are discussed based on the capacitance and conductance measurements at a low temperature and room temperature. 4H-SiC(0338) was found to have different energy distribution of the interface state density from the (0001) face. The shallow interface state density on (0338) is lower than on (0001) by a factor of 4 to 8.

36 citations




Journal ArticleDOI
TL;DR: In this paper, the Schottky barrier height of 4H and 6H SiC/Metal (Pt, Mo, Ti) contacts was investigated on the crystallographic face of the SiC epilayer.
Abstract: The Schottky barrier height of 4H and 6H SiC/Metal (Pt, Mo, Ti) contacts depe n s on the crystallographic face of the SiC epilayer. The breakdown fields of Sc h ttky contacts without edge terminations are also discussed. Introduction At ICSCRM’2001 we reported the initial results [1] of our detailed investigation of Schottky barriers on four different faces of 6H and 4H SiC homoepitaxial layers. At tha t time, we had available only data for Pt contacts. Also, the n-type doping concentration of the 6H SiC epitaxial layers was about 10 18 cm, which is far too high for our purposes. We have extended our work to include three metals: Pt, Mo and Ti; four faces on both 4H and 6H SiC epilayers: (0001) Si , ) 1 000 ( C, ) 00 1 1 ( and ) 10 2 1 ( ; and three measurement techniques: Current-Voltage (I-V), Capacitance-Voltage (C-V) and Internal Photoemission (IPE) at room tem perature. Our latest Schottky barriers show improved ideality factors (closer to unity) and reduce d leakage current. Experiment The preparation of the 4H and 6H SiC boule pieces was described previously [1]. The substr ate doping concentration was approximately 5×10 -1×10 cm for both 6H and 4H SiC. N-type homoepitaxial layers about 10 m thick were grown by cold-wall CVD at 1520oC. The doping concentrations are of order 10 15 cm for both polytypes of SiC. The surface morphology of the epilayers is: (0001) Si – smooth, small pits, H 2 etched pits, surface pit density 200-500 cm ; ) 1 000 ( C – smooth, occasional 3C hillocks, H 2 etched pits, hillock density 10-30 cm ; ) 00 1 1 ( elongated defects, scratches, hillocks, surface defect density 500-1000 cm ; ) 10 2 1 ( smooth, occasional screw-induced hillocks, hillock density 10-30 cm . On all faces the rms surface roughness measured by AFM is about 3-9 Å in areas without large scale surface defects. C-V and low temperature photoluminescence measurements indicate that donor concentrati ons a e in the range 1-3×10 15 cm, the samples are slightly doped with aluminum, but the compensation is low. Ni ohmic contacts were fabricated on the back sides of the samples by e-beam eva poration followed by annealing at 1000oC for ten minutes. Pt, Mo and Ti Schottky contacts were fa bricated by sputtering with Ar (0.9-2.0×10 -8 torr base pressure). Before deposition the samples were RCA cleaned, etched in HF for five minutes, rinsed in deionized water and dried in N 2 gas. The circular contacts are about 100 Å thick and 0.12 mm and 0.5 mm in diameter for Current-Voltage (I-V) an d Capacitance-Voltage (C-V) measurements, and 1.0 mm in diameter for interna l photoemission (IPE). The setups for I-V, C-V and IPE are discussed elsewhere [1, 2]. Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 705-708 doi:10.4028/www.scientific.net/MSF.433-436.705 © 2003 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-12/03/20,10:57:00) To obtain the reverse high voltage breakdown data, all devices were measured in the dark while immersed in Flourinert FC-77 fluid. I-V curves below 1100 V were taken using a Keithley 237 High-Voltage Source-Measure Unit, while I-V curves above 1100 V were taken on a Tektronix Model 371A digitizing curve tracer. The 237 unit measures DC steps and can resolve much lower reverse leakage current than the 371A. The digitizer records at least a couple of 60 Hz voltage sweeps. The data were collected prior to catastrophic failure. Because the work function of a metal can be anisotropic [3], the morphology and crystallographic orientation of the metal films were investigated using X-ray diffraction. Both symmetrical (angle of incidence = angle of reflection) and glancing angle (angle of incidence = 0.5o) 2θ/ω scans were obtained using a Philips X’pert with a Cu source ( λ = 1.54 Å) operated at 45 kV, 40 mA. An X-ray monochromator was used to eliminate K lines. A symmetrical angular scan shows the metal planes parallel to the sample surface, while a glancing angle scan reveals metal microcrystallites with other orientations. Pt and Mo metal films tend to show a dominant (111) and (110) line, respectively, for the symmetrical angle scan and multiple l ines for the glancing angle scan for all four SiC faces. These results suggest that P and Mo thin films form (111) and (110) textured structures, respectively, for all SiC surface orientat ions. We were not able to obtain satisfactory Ti X-ray data due to its low Z. Based on these results we neglect the role of differences in the metal work function in the analysis. Results and Discussion The standard approaches to extract the Schottky barrier height (SBH), assum ed to be uniform over the interface, from the data are the thermionic emission model for I-V and the photoe missi n current model for IPE [4]. Inhomogeneity [5] can be taken into account by integrat ing over an assumed Gaussian distribution (GD) of noninteracting local barriers [6], specif ied by a mean barrier height and a width. It is essential to include series resistance when applying the GD approach to I-V data in order to obtain values of the ideality factor n greater than unity. The obtained SBH is the mean value. The GD method enables a comparison of a set of contacts on the same sample having different ideality factors. Fig. 1 shows that the mean SBH obtained using the GD method is: 1) independent of the value 6H-SiC I-V Work-function [eV] 4.0 4.4 4.8 5.2 5.6 6.0 S ch ot tk y ba rr ie r he ig ht [e V ] 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 0001 Si 000-1 C 1-100 1-210 Ti (polycrystal) Mo (110) Pt (111) 4H-SiC I-V Work-function [eV] 4.0 4.4 4.8 5.2 5.6 6.0 S ch ot tk y ba rr ie r he ig ht [e V ] 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0001 Si 000-1 C 1-100 1-210 Ti (polycrystal) Mo (110) Pt (111) Fig. 3. SBH versus metal work function for four faces of 4H SiC obtained by forward I-V. Fig. 2. SBH versus metal work function for four faces of 6H SiC obtained by forward I-V. Ideality factor n 1.00 1.05 1.10 1.15 1.20 1.25 1.30 φ S [e V ] 0.95 1.00 1.05 1.10 1.15 1.20

19 citations


Journal ArticleDOI
TL;DR: In this article, the authors applied conventional transmission electron microscopy to study the nature of crystallographic defects under some types of surface morphological faults formed on a 4H-SiC film homoepitaxially grown on a (0001) off-cut substrate.
Abstract: Conventional transmission electron microscopy was applied to study the nature of crystallographic defects under some types of surface morphological faults formed on a 4H–SiC film homoepitaxially grown on a (0001) off-cut substrate "Wavy pit" faults consist of arrays of small surface cavities and half-loops of perfect dislocations expanding towards the direction of their Burgers vector "Carrot" and "comet" faults are accompanied by stacking faults The geometry of crystallographic defects under surface faults is closely related to the off-cut direction of the substrate Formation mechanisms of surface faults are discussed

19 citations


Journal ArticleDOI
TL;DR: In this paper, high-energy (MeV) implantation of Al+ or B+ into 4H-SiC epilayers has been investigated and a 3 μm pn junction was formed by multiple-step Al+ and B+ implantation with implantation energies up to 6.2 or 3.4 MeV, respectively.
Abstract: High-energy (MeV) implantation of Al+ or B+ into 4H-SiC epilayers has been investigated. A 3 μm deep pn junction was formed by multiple-step Al+ or B+ implantation with implantation energies up to 6.2 or 3.4 MeV, respectively. Rutherford backscattering channeling and cross-sectional transmission electron microscopy analyses have revealed residual damages in the implanted layers even after high-temperature annealing at 1600–1800 °C. Nevertheless, high electrical activation ratios over 90% have been achieved for both Al+- and B+-implanted layers by annealing at 1800 °C. Mesa pin diodes with a 15-μm-thick i layer formed by MeV implantation have exhibited high breakdown voltages of 2860–3080 V. The reverse characteristics of diodes have been substantially improved by increasing annealing temperature up to 1800 °C. The diode performance is discussed with the results of deep level analyses near the junctions.


Journal ArticleDOI
TL;DR: In this paper, a SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 m/spl Omega/cm/sup 2/ at room temperature.
Abstract: Characteristics of p-n junction fabricated by aluminum-ion (Al/sup +/) or boron-ion (B/sup +/) implantation and high-dose Al/sup +/-implantation into 4H-SiC (0001) have been investigated. By the combination of high-dose (4/spl times/10/sup 15/ cm/sup -2/) Al/sup +/ implantation at 500/spl deg/C and subsequent annealing at 1700/spl deg/C, a minimum sheet resistance of 3.6 k/spl Omega///spl square/ (p-type) has been obtained. Three types of diodes with planar structure were fabricated by employing Al+ or B+ implantation. B/sup +/-implanted diodes have shown higher breakdown voltages than Al/sup +/-implanted diodes. A SiC p-n diode fabricated by deep B+ implantation has exhibited a high breakdown voltage of 2900 V with a low on-resistance of 8.0 m/spl Omega/cm/sup 2/ at room temperature. The diodes fabricated in this study showed positive temperature coefficients of breakdown voltage, meaning avalanche breakdown. The avalanche breakdown is discussed with observation of luminescence.

Journal ArticleDOI
TL;DR: In this paper, the interface properties of MOS capacitors and MOSFETs were characterized using the (0001), (1120), and (0338) faces of 4H-SiC.
Abstract: The interface properties of MOS capacitors and MOSFETs were characterized using the (0001), (1120), and (0338) faces of 4H-SiC. (0001) and (1120) correspond to (111) and (110) in cubic structure. (0338) is semi-equivalent to (100). The interface states near the conduction band edge are discussed based on the capacitance and conductance measurements of n-type MOS capacitors at a low temperature and room temperature. The (0338) face indicated the smallest interface state density near the conduction band edge and highest channel mobility in n-channel MOSFETs among these faces.

Journal ArticleDOI
TL;DR: In this article, a SiC multiple-pn-junction structure was grown by atmospheric-pressure chemical vapor deposition using silane, propane and hydrogen, and the results were compared with those of secondary ion mass spectrometry (SIMS).
Abstract: Scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) of a SiC multiple-pn-junction structure are presented. The structure was grown by atmospheric-pressure chemical vapor deposition using silane, propane and hydrogen. Nitrogen and diborane were used for n- and p-type doping gases, respectively. The SCM and SSRM results are compared with those of secondary ion mass spectrometry (SIMS). The 0.2-µm-thick n-type layer and 0.3-µm-thick p-type layer with a doping level of 1.5 ×1017 cm-3 in the multiple pn-junction were clearly resolved by both SCM and SSRM as well as SIMS.

Journal ArticleDOI
TL;DR: In this paper, a profile of CVD grown 3C SiC on undulant (001) Si using low temperature photoluminescence (LTPL) was given.
Abstract: A description is given of the profiling of CVD grown 3C SiC on undulant (001) Si using low temperature photoluminescence (LTPL). Inelastic neutron scattering (INS) and X-ray Raman scattering (XRS) are compared for acoustical modes of 4H SiC. Schottky barrier heights are obtained for 4H and 6H SiC on different crystal faces using three different measuring techniques. Scanning electron microscopy (SEM) is used to display a variety of porous SiC morphologies achieved in n-type and p-type SiC. This paper is intended to be the introduction to the “CHARACTERIZATION” section of this volume. To serve this purpose we illustrate the subject matter with new results using four distinct experimental techniques.


Patent
02 Dec 2002
TL;DR: A lateral junction field effect transistor (LJFET) as discussed by the authors is a type of transistor that includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layers, and doped with p-type impurities more heavily than the second gate layer.
Abstract: A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.





Patent
02 Dec 2002
TL;DR: In this article, a lateral junction field effect transistor (LJFET) with a first gate electrode layer (18A), having a p-type impurity concentration higher than that of a second gate layer (12), is provided between source/drain region layers (6, 8) in a third semiconductor layer (13) extending into both the second and third layers.
Abstract: A lateral junction field-effect transistor is provided with a first gate electrode layer (18A). This first electrode layer, having a p-type impurity concentration higher than the impurity concentration of a second semiconductor layer (12), is provided between source/drain region layers (6, 8) in a third semiconductor layer (13) extending into both the second semiconductor layer (12) and the third semiconductor layer. The lower face of the first electrode layer extends into the second semiconductor layer (12). A second gate electrode layer (18B), containing p-type impuritoes having almost the same impurity concentration as that of the first gate electrode layer (18A) and the same potential, is provided between the source/drain region layers (6, 8) in a fifth semiconductor layer (15). The lower face of the second gate electrode layer extends into a fourth semiconductor layer (14). As a result, a lateral junction field-effect transistor is provided which has a structure for reducing the on-resistance while maintaining a favorable breakdown voltage performance.

Journal ArticleDOI
TL;DR: Z1 center concentration in 4H-SiC epilayers prepared by horizontal cold-wall chemical vapor deposition under various growth conditions were measured using deep-level transient Fourier spectroscopy with high sensitivity.
Abstract: Z1 center concentrations in 4H-SiC epilayers prepared by horizontal cold-wall chemical vapor deposition under various growth conditions were measured using deep-level transient Fourier spectroscopy with high sensitivity. It was found that the Z1 center concentration decreases with increasing carbon-to-silicon ratio in epitaxial growth. It is suggested that the Z1 center concentration is not related to the nitrogen donor concentration.





Journal ArticleDOI
TL;DR: In this article, the performance of 4H-SiC (03-38) epitaxial growth was investigated on non-standard faces with a low background doping concentration of 2∼3×1014 cm-3.
Abstract: Homoepitaxial growth, impurity doping, and diode fabrication on 4H-SiC(11–20) and (03–38) have been investigated. Although the efficiency of nitrogen incorporation is higher on the non-standard faces than on (0001), a low background doping concentration of 2∼3×1014 cm-3 can be achieved. On these faces, boron and aluminum are less effectively incorporated, compared to the growth on off-axis (0001). 4H-SiC(11–20) epilayers are micropipe-free, as expected. More interestingly, almost perfect micropipe closing has been realized in 4H-SiC (03–38) epitaxial growth. Ni/4H-SiC(11–20) and (03–38) Schottky barrier diodes showed promising characteritics of 3.36 kV-24 mΩcm2 and 3.28 kV–22 mΩcm2, respectively. The breakdown voltage of 4H-SiC(03–38) Schottky barrier diodes was significantly improved from 1 kV to above 2.5 kV by micropipe closing.