There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Power semiconductor device

Recent success with the fabrication of high-performance GaN-on-Si high-voltage HFETs has made this technology a contender for power electronic applications. This paper discusses the properties of GaN that make it an attractive alternative to established silicon and emerging SiC power devices. Progress in development of vertical power devices from bulk GaN is reviewed followed by analysis of the prospects for GaN-on-Si HFET structures. Challenges and innovative solutions to creating enhancement-mode power switches are reviewed.

https://iopscience.iop.org/article/10.1088/0268-1242/28/7/074011/pdf

Gallium nitride devices for power electronic applications

A novel method for fabricating trench structures on GaN was developed. A smooth non-polar (1100) plane was obtained by wet etching using tetramethylammonium hydroxide (TMAH) as the etchant. A U-shape trench with the (1100) plane side walls was formed with dry etching and the TMAH wet etching. A U-shape trench gate metal oxide semiconductor field-effect transistor (MOSFET) was also fabricated using the novel etching technology. This device has the excellent normally-off operation of drain current–gate voltage characteristics with the threshold voltage of 10 V. The drain breakdown voltage of 180 V was obtained. The results indicate that the trench gate structure can be applied to GaN-based transistors.

https://iopscience.iop.org/article/10.1143/APEX.1.021104/pdf

GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

We fabricated a vertical insulated gate AlGaN/GaN heterojunction field-effect transistor (HFET), using a free-standing GaN substrate. This HFET has apertures through which the electron current vertically flows. These apertures were formed by dry etching the p-GaN layer below the gate electrodes and regrowing n--GaN layer without mask. The HFET exhibited a specific on-resistance of as low as 2.6 mΩ·cm2 with a threshold voltage of -16 V. This HFET would be a prototype of a GaN-based high-power switching device.

https://iopscience.iop.org/article/10.1143/JJAP.46.L503/pdf

A Vertical Insulated Gate AlGaN/GaN Heterojunction Field-Effect Transistor

PROBLEM TO BE SOLVED: To increase a withhold voltage of a vertical MOS filed effect transistor 1. SOLUTION: This vertical MOS field effect transistor 1 has a super junction structure 13. The super junction structure 13 is a structure wherein first conductive semiconductor regions and second conductive semiconductor regions are arranged alternately in a direction vertical to a current flow in a drift region. An insulating region 35 is positioned outside a silicon single crystal region (P-type silicon single crystal region 15) located at an end of the super junction structure 13. The insulating region 35 is formed by burying a silicon oxide film in a trench 33. COPYRIGHT: (C)2001,JPO

Vertical semiconductor device

Magnesium ion implantation has been performed on a GaN substrate, whose surface has a high thermal stability, thus allowing postimplantation annealing without the use of a protective layer. The current–voltage characteristics of p–n diodes fabricated on GaN showed distinct rectification at a turn-on voltage of about 3 V, although the leakage current varied widely among the diodes. Coimplantation with magnesium and hydrogen ions effectively suppressed the leakage currents and device-to-device variations. In addition, an electroluminescence band was observed at wavelengths shorter than 450 nm for these diodes. These results provide strong evidence that implanted magnesium ions create acceptors in GaN.

https://iopscience.iop.org/article/10.7567/APEX.10.016501/pdf

P-type doping of GaN(000\bar{1}) by magnesium ion implantation

A semiconductor device is formed by a first layer 32 composed of AlGaN, a second layer 42 composed of GaN, a gate electrode 34, a source electrode 38, and a drain electrode 28. The first layer 32 has a region 32 a formed between the gate electrode 34 and the second layer 42. A channel is formed in the vicinity of the boundary 24 of the first layer 32 and the second layer 42. The second layer 42 has p-type conductivity and is in contact with the source electrode 38. When electrons flow in the channel, the electrons collide with surrounding atoms, and holes are formed. If holes are accumulated inside the semiconductor device, the presence of the accumulated holes causes dielectric breakdown. In the semiconductor device of the invention, holes are discharged to the outside of the device thorough the second layer 42 and the source electrode 38, and accumulation of holes can be prevented.

Tsutomu Uesugi

Papers

GaN-Based Trench Gate Metal Oxide Semiconductor Field-Effect Transistor Fabricated with Novel Wet Etching

A Vertical Insulated Gate AlGaN/GaN Heterojunction Field-Effect Transistor

Vertical semiconductor device

P-type doping of GaN(000\bar{1}) by magnesium ion implantation

Group III nitride semiconductor device