C
C. Le Royer
Researcher at University of Grenoble
Publications - 14
Citations - 184
C. Le Royer is an academic researcher from University of Grenoble. The author has contributed to research in topics: Metal gate & Electron mobility. The author has an hindex of 7, co-authored 14 publications receiving 165 citations. Previous affiliations of C. Le Royer include Commissariat à l'énergie atomique et aux énergies alternatives.
Papers
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Journal ArticleDOI
High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate
K. Romanjek,Louis Hutin,C. Le Royer,A. Pouydebasque,Marie-Anne Jaud,Claude Tabone,E. Augendre,Loic Sanchez,J.M. Hartmann,H. Grampeix,V. Mazzocchi,S. Soliveres,R. Truche,Laurent Clavelier,P. Scheiblin,X. Garros,G. Reimbold,Maud Vinet,Fabien Boulanger,Simon Deleonibus +19 more
TL;DR: In this paper, the authors demonstrate for the first time 70nm gate length gate length TiN/HfO 2 pMOSFETs on 200mm GeOI wafers, with excellent performance: I ON Â= 260μA/μm and I OFF Â = 500 Ã 1.0 Â V (without germanide).
Proceedings ArticleDOI
Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS
Olivier Weber,Y. Bogumilowicz,Thomas Ernst,J.M. Hartmann,F. Ducroquet,Francois Andrieu,Cecilia Dupre,Laurent Clavelier,C. Le Royer,Nikolay Cherkashin,Martin Hÿtch,D. Rouchon,H. Dansas,A.M. Papon,V. Carron,Claude Tabone,Simon Deleonibus +16 more
TL;DR: In this paper, the same process for a dual channel integration scheme was used to achieve symmetric n-and p-MOSFET IDsat performance with high-k gate dielectric.
Proceedings ArticleDOI
Boron and Phosphorus dopant activation in Germanium using laser annealing with and without preamorphization implant
V. Mazzocchi,C. Sabatier,M. Py,Karim Huet,C. Boniface,J.P. Barnes,Louis Hutin,V. Delayer,D. Morel,Maud Vinet,C. Le Royer,J. Venturini,K. Yckache +12 more
TL;DR: In this paper, an industrial tool was used to achieve electrical activation levels up to 1.2×1020 cm−3 for P implant in amorphized Germanium and 0.95 J/cm² in crystalline Germanium (c-Ge).
Journal ArticleDOI
Ultrathin (5 nm) SiGe-On-Insulator with high compressive strain (−2 GPa): From fabrication (Ge enrichment process) to in-depth characterizations
F. Glowacki,C. Le Royer,Y. Morand,J. M. Pedini,Thibaud Denneulin,David Cooper,Jean-Paul Barnes,P. Nguyen,Denis Rouchon,Jean-Michel Hartmann,Olivier Gourhant,E. Baylac,Yves Campidelli,D. Barge,O. Bonnin,Walter Schwarzenbach +15 more
TL;DR: In this paper, a 5-nm SiGe-On-Insulator (SGOI) substrate was used as the channel of a fully depleted (FD) p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFET).
Proceedings ArticleDOI
First demonstration of 3D SRAM through 3D monolithic integration of InGaAs n-FinFETs on FDSOI Si CMOS with inter-layer contacts
Veeresh Deshpande,Herwig Hahn,Eamon O'Connor,Yannick Baumgartner,Marilyne Sousa,Daniele Caimi,H. Boutry,Julie Widiez,L. Brevard,C. Le Royer,Maud Vinet,Jean Fompeyrine,Lukas Czornomaz +12 more
TL;DR: In this article, the authors demonstrate the 3D integration of In 0.53 GaAs nFETs on FDSOI Si CMOS featuring short-channel Replacement Metal Gate (RMG) InGaAs n-FinFET on the top layer and Gate-First Si-CMOS on the bottom layer with TiN/W inter-layer contacts.