Showing papers by "Vijaykrishnan Narayanan published in 2014"

Tunnel FET RF Rectifier Design for Energy Harvesting Applications

Abstract: Radio-frequency (RF)-powered energy harvesting systems have offered new perspectives in various scientific and clinical applications such as health monitoring, bio-signal acquisition, and battery-less data-transceivers. In such applications, an RF rectifier with high sensitivity, high power conversion efficiency (PCE) is critical to enable the utilization of the ambient RF signal power. In this paper, we explore the high PCE advantage of the steep-slope III-V heterojunction tunnel field-effect transistor (HTFET) RF rectifiers over the Si FinFET baseline design for RF-powered battery-less systems. We investigate the device characteristics of HTFETs to improve the sensitivity and PCE of the RF rectifiers. Different topologies including the two-transistor (2-T) and four-transistor (4-T) complementary-HTFET designs, and the n-type HTFET-only designs are evaluated with design parameter optimizations to achieve high PCE and high sensitivity. The performance evaluation of the optimized 4-T cross-coupled HTFET rectifier has shown an over 50% PCE with an RF input power ranging from -40 dBm to -25 dBm, which significantly extends the RF input power range compared to the baseline Si FinFET design. A maximum PCE of 84% and 85% has been achieved in the proposed 4-T N-HTFET-only rectifier at -33.7 dBm input power and the 4-T cross-coupled HTFET rectifier at -34.5 dBm input power, respectively. The capability of obtaining a high PCE at a low RF input power range reveals the superiority of the HTFET RF rectifiers for battery-less energy harvesting applications.

Electrical Noise in Heterojunction Interband Tunnel FETs

Abstract: We present an analysis of electrical noise in III-V heterojunction TFET (HTFET) Using numerical simulations, random telegraph noise (RTN) amplitude induced by a single charge trap is investigated with regard to trap location, electron band-to-band-generation rate, bias, and transistor size It is found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction HTFET exhibits 40% less relative RTN amplitude at 03 V at gate lengths around 20 nm, over subthreshold Si-FinFET RTN of HTFET at VGS=0 V is higher for a trap location at source-channel tunnel junction To analyze flicker, shot, and thermal noise, we created transistor level Verilog-A-based electrical noise models The results indicate HTFETs competitive noise performance in megahertz frequency range, over Si-FinFET In the range 10 GHz or more with operating voltages exceeding 03 V, HTFET input noise is worse due to the dominance of shot noise A differential amplifier with active load is used to examine the electrical noise performance at circuit level We emphasize that high intrinsic gain, drive current, and output resistance of HTFET can be used to achieve superior mixed signal performance metrics in HTFET design over Si-FinFET design, at an improved electrical noise performance

Soft-Error Performance Evaluation on Emerging Low Power Devices

Abstract: Radiation-induced single-event upset (SEU) has become a key challenge for cloud computing. The proposed introduction of low bandgap materials (Ge, III-Vs) as channel replacement and steep switching devices for low-voltage applications may induce radiation reliability issues due to their low ionization energy and device architecture. In this paper, the soft-error generation and propagation in Si FinFET, III-V FinFET, and III-V Hetero-junction tunnel FET (HTFET) are investigated using device and circuit simulation. III-V FinFET shows enhanced charge collection compared with Si FinFET, whereas HTFET shows significant reduction of the bipolar gain effect and charge collection. Soft-error rate (SER) evaluation methodology has been proposed for these emerging devices based on the critical LET extraction. SRAM bit flip, electrical masking effect, and latching window masking effect have been analyzed with supply voltage scaling. The SER evaluation of SRAM and logic shows that HTFET-based circuits are promising for radiation resilient ultra-low power applications. III-V FinFET shows increased SER for SRAM for ${\rm V}_{\rm DD}$ range of 0.3–0.8 Vand reduced logic SER below 0.5 V compared with Si FinFET.

Rf-powered systems using steep-slope devices

Abstract: Steep-slope tunnel devices promise new opportunities in ultra-low-power computing. This paper focuses on how steep-slope devices can enhance efficiencies of harvesting ambient RF energy and improve power efficiency of analog and digital computational blocks.

Steep Slope Devices: Enabling New Architectural Paradigms

Abstract: The existence of domains where traditional CMOS processors are inefficient has been well-documented in the current literature In particular, the inefficiency of general purpose CMOS designs operating at very low supply voltages is well-known, and steep sub-threshold slope technologies, such as Tunneling Field Effect Transistors (TFETs), have been demonstrated as a viable alternative for the low-voltage operation domain However, restricting the design space of steep slope technology-based processors to near-threshold or sub-threshold general purpose processors does the technology a disserviceSteep slope (SS) architectures can simultaneously expand the frontiers of viable computers at both ends of the energy scale: On the one hand, SS architectures enable ultra-low power sensor nodes and wearable technology, while on the other, they are applicable to high powered servers and high performance computing engines We demonstrate the benefits of adapting this technology in such non-conventional domains, while attempting to address the major challenges encountered We explore the effect of noise and variations at various levels of abstraction, ranging from the device to the architecture, and examine various techniques to overcome them

Modeling steep slope devices: from circuits to architectures

Abstract: Steep Slope devices, with Heterojunction Tunnel FETs (TFETs) in particular, have been proposed as a viable solution to overcome the subthreshold slope limitation in existing CMOS technology and achieve ultra-low voltage operation with acceptable performance. However, state-of-the-art FinFET technologies continue to demonstrate superior performance than steep slope devices in application domains demanding peak single threaded performance. In this context, we examine different computing paradigms where TFET technologies can be used, not just as a `drop in' replacement, but as an additional parameter to augment the architectural design space. This greatly widens the scope of optimizations for performance and power. We investigate the tradeoffs between device and architectures in general purpose processors when performance, power and temperature are individually constrained. We also synthesize examples of domain-specific accelerators used in computer vision using in-house TFET standard cell libraries to demonstrate the energy benefits of designing TFET-based accelerators. We demonstrate that synthesizing these accelerators using TFETs reduces energy by over 6X in comparison to an equivalent iso-voltage CMOS-based design and by over 30% in comparison to an iso-performance CMOS design.

Video analytics using beyond CMOS devices

Abstract: The human vision system understands and interprets complex scenes for a variety of visual tasks in real-time while consuming less than 20 Watts of power. The holistic design of artificial vision systems that will approach and eventually exceed the capabilities of human vision systems is a grand challenge. The design of such a system needs advances in multiple disciplines. This paper focuses on advances needed in the computational fabric and provides an overview of a new-genre of architectures inspired by advances in both the understanding of the visual cortex and the emergence of devices with new mechanisms for state computations.

Enabling power-efficient designs with III-V tunnel FETs

Abstract: III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, unidirectional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and architectural level. Index Terms — Steep-slope devices, ultra-low power, lowvoltage, III-V Tunnel FET (TFET).

A hardware accelerated multilevel visual classifier for embedded visual-assist systems

Abstract: Embedded visual assist systems are emerging as increasingly viable tools for aiding visually impaired persons in their day-to-day life activities. Novel wearable devices with imaging capabilities will be uniquely positioned to assist visually impaired in activities such as grocery shopping. However, supporting such time-sensitive applications on embedded platforms requires an intelligent trade-off between accuracy and computational efficiency. In order to maximize their utility in real-world scenarios, visual classifiers often need to recognize objects within large sets of object classes that are both diverse and deep. In a grocery market, simultaneously recognizing the appearance of people, shopping carts, and pasta is an example of a common diverse object classification task. Moreover, a useful visual-aid system would need deep classification capability to distinguish among the many styles and brands of pasta to direct attention to a particular box. Exemplar Support Vector Machines (ESVMs) provide a means of achieving this specificity, but are resource intensive as computation increases rapidly with the number of classes to be recognized. To maintain scalability without sacrificing accuracy, we examine the use of a biologically-inspired classifier (HMAX) as a front-end filter that can narrow the set of ESVMs to be evaluated. We show that a hierarchical classifier combining HMAX and ESVM performs better than either of the two individually. We achieve 12% improvement in accuracy over HMAX and 4% improvement over ESVM while reducing computational overhead of evaluating all possible exemplars.

A task-oriented vision system

Abstract: Recently, biologically inspired vision systems have been the focus of intense research effort to emulate the high energy-efficiency, performance and robustness of mammalian vision systems. However, previous vision accelerators have only focused on speeding up computationally intense portions of the system without exploiting effects seen in the human brain that demonstrate the task influence in the vision mechanism. In this paper, we propose a task-oriented two-level vision system which is composed of Saliency and SURF. To the best of our knowledge, our design is the first embedded system that utilizes task influence in the computation of visual attention and recognition. As a result, we show that the new system can achieve at most 12.75% accuracy improvement while saving 25% computation work.