Showing papers by "Yao-Wen Chang published in 2008"
TL;DR: This work proposes a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework and uses the conjugate gradient method to find better macro positions.
Abstract: In addition to wirelength, modern placers need to consider various constraints such as preplaced blocks and density. We propose a high-quality analytical placement algorithm considering wirelength, preplaced blocks, and density based on the log-sum-exp wirelength model proposed by Naylor and the multilevel framework. To handle preplaced blocks, we use a two-stage smoothing technique, i.e., Gaussian smoothing followed by level smoothing, to facilitate block spreading during global placement (GP). The density is controlled by white-space reallocation using partitioning and cut-line shifting during GP and cell sliding during detailed placement. We further use the conjugate gradient method with dynamic step-size control to speed up the GP and macro shifting to find better macro positions. Experimental results show that our placer obtains very high-quality results.
260 citations
TL;DR: The first network-flow-based routing algorithm that can concurrently route a set of noninterfering nets for the droplet routing problem on biochips is presented and is presented as the first polynomial-time algorithm for simultaneous routing and scheduling using the global-routing paths with a negotiation- based routing scheme.
Abstract: Due to recent advances in microfluidics, digital microfluidic biochips are expected to revolutionize laboratory procedures. One critical problem for biochip synthesis is the droplet routing problem. Unlike traditional very large scale integration routing problems, in addition to routing path selection, the biochip routing problem needs to address the issue of scheduling droplets under practical constraints imposed by the fluidic property and timing restriction of synthesis results. In this paper, we present the first network-flow-based routing algorithm that can concurrently route a set of noninterfering nets for the droplet routing problem on biochips. We adopt a two-stage technique of global routing followed by detailed routing. In global routing, we first identify a set of noninterfering nets and then adopt the network-flow approach to generate optimal global-routing paths for nets. In detailed routing, we present the first polynomial-time algorithm for simultaneous routing and scheduling using the global-routing paths with a negotiation-based routing scheme. Our algorithm targets at both the minimization of cells used for routing for better fault tolerance and minimization of droplet transportation time for better reliability and faster bioassay execution. Experimental results show the robustness and efficiency of our algorithm.
103 citations
08 Jun 2008
TL;DR: This paper proposes the first droplet routing algorithm that directly solves the problem of routing in cross-referencing biochips under the more scalable cross- referencingBiochip paradigm, which uses row/column addressing scheme to activate electrodes.
Abstract: Due to recent advances in microfluidics technology, digital microfluidic biochips and their associated CAD problems have gained much attention, most of which has been devoted to direct-addressing biochips. In this paper, we solve the droplet routing problem under the more scalable cross-referencing biochip paradigm, which uses row/column addressing scheme to activate electrodes. We propose the first droplet routing algorithm that directly solves the problem of routing in cross-referencing biochips. The main challenge of this type of biochips is the electrode interference which prevents simultaneous movement of multiple droplets. We first present a basic integer linear programming (ILP) formulation to optimally solve the droplet routing problem. Due to its complexity, we also propose a progressive ILP scheme to determine the locations of droplets at each time step. Experimental results demonstrate the efficiency and effectiveness of our progressive ILP scheme on a set of practical bio assays.
78 citations
TL;DR: A new full-chip gridless routing system considering double-via insertion for yield enhancement and a new redundant-via aware detailed maze routing algorithm (which could be applied to both gridless and grid-based routing).
Abstract: As the technology node advances into the nanometer era, via-open defects are one of the dominant failures due to the copper cladding process. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the postlayout stage. The increasing design complexity, however, leaves very limited space for postlayout optimization. It is thus desirable to consider the double-via insertion at both the routing and postrouting stages. In this paper, we present a new full-chip gridless routing system considering double-via insertion for yield enhancement. To fully consider double vias, the router applies a novel two-pass, bottom-up routability-driven routing framework and features a new redundant-via aware detailed maze routing algorithm (which could be applied to both gridless and grid-based routing). We also propose a graph-matching based post-layout double-via insertion algorithm to achieve a higher insertion rate. In particular, the algorithm is optimal for grid-based routing with up to three routing layers and the stacked-via structure. Experiments show that our methods significantly improve the via count, number of dead vias, double-via insertion rates, and running times.
67 citations
TL;DR: This paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction and shows that the algorithm results in significantly shorter wirelengths than all state-of-the-art works.
Abstract: Given a set of pins and a set of obstacles on a plane, an obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) connects these pins, possibly through some additional points (called the Steiner points), and avoids running through any obstacle to construct a tree with a minimal total wirelength. The OARSMT problem becomes more important than ever for modern nanometer IC designs which need to consider numerous routing obstacles incurred from power networks, prerouted nets, IP blocks, feature patterns for manufacturability improvement, antenna jumpers for reliability enhancement, etc. Consequently, the OARSMT problem has received dramatically increasing attention recently. Nevertheless, considering obstacles significantly increases the problem complexity, and thus, most previous works suffer from either poor quality or expensive running time. Based on the obstacle-avoiding spanning graph, this paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction. Unlike previous heuristics, our algorithm guarantees to find an optimal OARSMT for any two-pin net and many higher pin nets. Extensive experiments show that our algorithm results in significantly shorter wirelengths than all state-of-the-art works.
63 citations
08 Jun 2008
TL;DR: A new direction/technique is proposed, called net overlapping removal, to optimize the routability during placement, and a Gaussian smoothing technique is proposed to handle the challenging macro porosity issue, arising in modern mixed-size designs with large macros.
Abstract: Routability is a challenging cost metric for modern large-scale mixed-size placement. Most existing routability-driven placement algorithms apply whitespace allocation to relieve the routing congestion. Nevertheless, we observe that whitespace allocation might worsen the routability of a placement. To remedy this deficiency, we propose in this paper a new direction/technique, called net overlapping removal, to optimize the routability during placement. Unlike most previous works that allocate whitespace among blocks, our approach moves nets apart from congested regions to improve the chip routability. To apply the net overlapping removal technique, we generalize a net bounding-box based congestion evaluation model to handle practical routing constraints and speed up the routability optimization during placement. We further propose a Gaussian smoothing technique to handle the challenging macro porosity issue, arising in modern mixed-size designs with large macros that require to preserve routing resources for inner routing of the macros. Experimental results show that our approaches lead to significantly better routability and running time than previous works for mixed-size placement.
52 citations
TL;DR: This paper presents an efficient algorithm with some theoretical optimality guarantees for the OARSMT construction and shows that the algorithm results in significantly shorter wirelengths than all state-of-the-art works.
Abstract: Given a set of pins and a set of obstacles on routing layers, a multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges within layers and vias between layers and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The ML-OARSMT problem is very important for many very large scale integration designs with pins being located in multiple routing layers that contain numerous routing obstacles incurred from IP blocks, power networks, prerouted nets, etc. As a fundamental problem with extensive practical applications to routing and wirelength/congestion/timing estimations in early design stages, it is desired to develop an effective algorithm for the ML-OARSMT problem to facilitate the design flow. However, there is no existing work on this ML-OARSMT problem. In this paper, we first formulate the ML-OARSMT problem with rectangular obstacles and then identify key different properties of this problem from its single-layer counterpart. Based on the multilayer obstacle-avoiding spanning graph, we present the first algorithm to solve the ML-OARSMT problem. Our algorithm can guarantee an optimal solution for any two-pin net and many multiple-pin nets. Experiments show that our algorithm results in 33% smaller total costs on average than a construction-by-correction heuristic which is widely used for Steiner-tree construction in the recent literature.
47 citations
10 Nov 2008
TL;DR: This paper presents the first work in the literature to handle the multiple Re-Distribution Layer (RDL) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design and demonstrates that the router can achieve 100% routability and the optimal routing wirelength under reasonable CPU times.
Abstract: The area-I/O flip-chip package provides a high chip-density solution to the demand of more I/Opsilas in VLSI designs; it can achieve smaller package size, shorter wirelength, and better signal and power integrity. In this paper, we introduce the routing problem for chip and package co-design and present the first work in the literature to handle the multiple Re-Distribution Layer (RDL) routing problem for flip-chip designs, considering pin and layer assignment, total wirelength minimization, and chip-package co-design. Our router adopts a two-stage technique of global routing followed by RDL routing. The global routing assigns each block port to a unique bump pad via an I/O pad and decides the RDL routing among I/O pads and bump pads. Based on the minimum-cost maximum-flow algorithm, we can guarantee 100% RDL routing completion after the assignment and the optimal solution with the minimum wirelength. The RDL routing efficiently distributes the routing points between two adjacent bump pads and then generates a 100% routable sequence to complete the routing. Experimental results based on 10 industry designs demonstrate that our router can achieve 100% routability and the optimal routing wirelength under reasonable CPU times, while related works cannot.
45 citations
TL;DR: A new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates and significantly reduces the average half-perimeter wirelength, and the routing overflows by 13 times compared with Capo 10.2, implying that the macro placer leads to much higher routability.
Abstract: In this paper, we present a new multipacking-tree (MP-tree) representation for macro placements to handle modern mixed-size designs with large macros and high chip utilization rates. Based on binary trees, the MP-tree is very efficient, effective, and flexible for handling macro placements with various constraints. Given a global placement that already considers the areas and the interconnections among standard cells and macros, our MP-tree-based macro placer optimizes macro positions, minimizes the macro displacement from the initial macro positions, and maximizes the area of the chip center for standard-cell placement and routing. Experiments based on the Proceedings of the 2006 International Symposium on Physical Design placement contest benchmarks and Faraday benchmarks show that our macro placer combined with APlace 2.0, Capo 10.2, mPL6, or NTUplace3 for a standard-cell placement outperforms these state-of-the-art academic mixed-size placers alone by large margins in robustness and quality. In addition to wirelength, experiments on four real industrial designs with large macros and high utilization rates show that our method significantly reduces the average half-perimeter wirelength by 35 %, the average routed wirelength by 55 %, and the routing overflows by 13 times compared with Capo 10.2, implying that our macro placer leads to much higher routability.
42 citations
10 Nov 2008
TL;DR: A more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing and a new global router that features two novel routing algorithms for congestion optimization, namely least-flexibility-first routing and multi-source multi-sink escaping-point routing.
Abstract: Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, we present in this paper a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing. With this congestion metric, we develop a new global router that features two novel routing algorithms for congestion optimization, namely least-flexibility-first routing and multi-source multi-sink escaping-point routing. The least-flexibility-first routing processes the nets with the least flexibility first, facilitating a quick prediction of congestion hot spots for the subsequent nets. Enjoying lower time complexity than traditional maze and A*-search routing, in particular, the linear-time escaping-point routing guarantees to find the optimal solution and achieves the theoretical lower-bound time complexity. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage, which can benefit and correctly guide subsequent detailed routing.
38 citations
08 Jun 2008
TL;DR: An efficient, accurate, and economical analytical formula for intensity computation is presented and the first modeling of postlayout OPC based on a quasi-inverse lithography technique is developed, providing key insights into a new direction for post layout OPC modeling during routing.
Abstract: Due to the sub-wavelength lithography, manufacturing sub-90 nm feature sizes require intensive use of resolution-enhancement techniques, among which optical proximity correction (OPC) is the most popular technique in industry. Considering the OPC effects during routing can significantly alleviate the cost of post-layout OPC operations. In this paper, we present an efficient, accurate, and economical analytical formula for intensity computation and develop the first modeling of post-layout OPC based on a quasi- inverse lithography technique. Extensive simulations with SPLAT, the golden lithography simulator in academia and industry, show that our intensity formula has high fidelity. Incorporating the OPC costs computed by the quasi-inverse lithography technique for our post-layout OPC modeling into a router, the router can be guided to maximize the effects of the correction. Compared with a rule- based OPC method, the experimental results show that our approach can achieve 14% and 16% reductions in the maximum and average layout distortions, respectively.
TL;DR: Experimental results show that the IMF obtains the best published fixed-outline floorplanning results with the smallest average wirelength for the Microelectronics Center of North Carolina/Gigascale Systems Research Center benchmarks, and scales very well as the circuit size increases.
Abstract: We present in this paper a new interconnect-driven multilevel floorplanner, called interconnect-driven multilevel-floorplanning framework (IMF), to handle large-scale building-module designs. Unlike the traditional multilevel framework that adopts the ldquoLambda-shapedrdquo framework (inaccurately called the ldquoV-cyclerdquo framework in the literature): bottom-up coarsening followed by top-down uncoarsening, the IMF, in contrast, works in the ldquoV-shapedrdquo manner: top-down uncoarsening (partitioning) followed by bottom-up coarsening (merging). The top-down partitioning stage iteratively partitions the floorplan region based on min-cut bipartitioning with exact net-weight modeling to reduce the number of global interconnections and, thus, the total wirelength. Then, the bottom-up merging stage iteratively applies fixed-outline floorplanning using simulated annealing for all regions and merges two neighboring regions recursively. Experimental results show that the IMF obtains the best published fixed-outline floorplanning results with the smallest average wirelength for the Microelectronics Center of North Carolina/Gigascale Systems Research Center benchmarks. In particular, IMF scales very well as the circuit size increases. The V-shaped multilevel framework outperforms the Lambda-shaped one in the optimization of global circuit effects, such as interconnection and crosstalk optimization, since the V-shaped framework considers the global configuration first and then processes down to local ones level by level, and thus, the global effects can be handled at earlier stages. The V-shaped multilevel framework is general and, thus, can be readily applied to other problems.
10 Nov 2008
TL;DR: A constraint graph-based macro placement algorithm that removes macro overlaps and optimizes macro positions for modern mixed-size circuit designs and can consistently and significantly reduce the wirelengths for designs with different utilization rates is proposed, implying that the macro placer is robust and has very high quality.
Abstract: In this paper, we propose a constraint graph-based macro placement algorithm that removes macro overlaps and optimizes macro positions for modern mixed-size circuit designs. Improving over the constraint graph by working only on its essential edges without loss of the solution quality, our algorithm can search for high-quality macro placement solutions effectively and efficiently. Instead of packing macros along chip boundaries like most recent previous work, our placer can determine a non-compacted macro placement by linear programming and placement region cost evaluation and handle various placement constraints/objectives. Compared with various leading academic macro placers, our algorithm can consistently and significantly reduce the wirelengths for designs with different utilization rates, implying that our macro placer is robust and has very high quality.
10 Nov 2008
TL;DR: Experimental results show that the first routing algorithm in the literature for chip-package-board co-design with differential-pair considerations can achieve 100% routability and the optimal global-routing wirelength and satisfy all differential- Pair constraints, under reasonable CPU times, whereas recent related work results in much inferior solution quality.
Abstract: Nanometer effects have complicated the designs of chips as well as packages and printed circuit boards (PCBpsilas). In order to improve the performance, convergence, and signal integrity of the design, chip-package-board co-design is strongly recommended by industry. In this paper, we present the first routing algorithm in the literature for chip-package-board co-design with differential-pair considerations. Our algorithm is based on linear programming and integer linear programming and guarantees to find an optimal solution for the addressed problem. It first creates global-routing paths among chips, packages, and a PCB. Without loss of the solution optimality, our routing formulation can reduce the numbers of integer variables (constraints) by 95% (99%) on average. Then, any-angle routing is applied to complete the routing. Experimental results based on five real industry designs show that our router can achieve 100% routability and the optimal global-routing wirelength and satisfy all differential-pair constraints, under reasonable CPU times, whereas recent related work results in much inferior solution quality.
TL;DR: This paper proposes the first metal-density-driven (MDD) placement algorithm to reduce chemical-mechanical planarization/polishing (CMP) variation and achieve higher routability and efficiently estimate metal density and thickness.
Abstract: In this paper, we propose the first metal-density-driven (MDD) placement algorithm to reduce chemical-mechanical planarization/polishing (CMP) variation and achieve higher routability. To efficiently estimate metal density and thickness, we first apply a probabilistic routing model and then a predictive CMP model to obtain the metal-density map. Based on the metal-density map, we use an analytical placement framework to spread blocks to reduce metal-density variation. Experimental results based on BoxRouter and NTUgr show that our method can effectively reduce the CMP variation. By using our MDD placement, for example, the topography variation can be reduced by up to 38% (23%) and the number of dummy fills can be reduced by up to 14% (8%), compared with those using wirelength-driven (cell-density-driven) placement. The results of our MDD placement can also lead to better routability.
13 Apr 2008
TL;DR: This paper proposes the first metal-density-driven (MDD) placement algorithm to reduce chemical-mechanical planarization/polishing (CMP) variation and achieve higher routability and efficiently estimate metal density and thickness.
Abstract: In this paper, we propose the first metal-density driven placement algorithm to reduce CMP variation and achieve higher routability. Based on an analytical placement framework, we use a probabilistic routing model to estimate the wire density during the placement. Then, the metal density and thickness are predicted by a predictive CMP model. The spreading forces are adjusted according to the metal density map to reduce the metal density variation. Experimental results show that our method reduces the topography variation by 12% and the number of dummy fills by 6% and achieves much better routability, compared with wirelength-driven placement
TL;DR: A novel charge-based capacitance measurement technique is used and the split capacitance-voltage method is used to extract the intrinsic of MOSFET devices, and the mobility of devices with various channel widths is extracted.
Abstract: The shallow trench isolation (STI) stress effect along the length direction on short-channel MOSFET devices has already been widely studied. However, the effect along the width direction has seldom been specifically analyzed. In this paper, we combine a novel charge-based capacitance measurement technique, which is used to extract the intrinsic of MOSFET devices, and the split capacitance-voltage method to extract the mobility of devices with various channel widths. Although it is already known that under the influence of compressive STI stress along the width direction the mobility of both NMOS and PMOS devices will degrade with decreasing width, it is the first time to quantify the impact of this STI stress component on MOSFET devices.
TL;DR: This paper introduces the analysis problem for ESD protection in circuit design, model the circuit as a constraint graph, decompose the ESD connected components (ECCs) linked with the pads, and applies breadth-first search to identify the ECCs in each constraint graph and, thus, the current paths.
Abstract: The electrostatic discharge (ESD) problem has become a challenging reliability issue in nanometer-circuit design. High voltages that resulted from ESD might cause high current densities in a small device and burn it out, so on-chip protection circuits for IC pads are required. To reduce the design cost, the protection circuit should be added only for the IC pads with an ESD current path, which causes the ESD current path analysis problem. In this paper, we first introduce the analysis problem for ESD protection in circuit design. We then model the circuit as a constraint graph, decompose the ESD connected components (ECCs) linked with the pads, and apply breadth-first search (BFS) to identify the ECCs in each constraint graph and, thus, the current paths. Experimental results show that our algorithm can very efficiently and economically detect all ESD paths. For example, our algorithm can detect all ESD paths in a circuit with more than 1.3 million vertices in 1.39 s and consume only 44-MB memory on a 3.0-GHz Intel Pentium 4 PC. To the best of our knowledge, our algorithm is the first point tool available to the public for the ESD analysis.
TL;DR: A polynomial-time antenna violation detection/fixing algorithm by simultaneous diode and jumper insertion with minimum cost, which is based on a minimum-cost network-flow formulation is given.
Abstract: As technology enters the nanometer territory, the antenna effect plays an important role in determining the yield and reliability of a VLSI circuit. Diode and jumper insertions are the most effective techniques to fix the antenna effect. However, due to the increasing design complexity and the limited routing resource, applying diode or jumper insertion alone cannot achieve a high antenna fixing rate. In this paper, we give a polynomial-time antenna violation detection/fixing algorithm by simultaneous diode and jumper insertion with minimum cost, which is based on a minimum-cost network-flow formulation. Experimental results show that our algorithm consistently achieves much higher antenna fixing rates than the state-of-the-art jumper and diode insertion algorithms alone.
23 Apr 2008
TL;DR: In this paper, the authors developed a novel sensitivity formulation with a more global view on the gate swapping effects, which can effectively reduce leakage power by up to 74.4% compared with the state-of-the-art sensitivity-based method.
Abstract: With the technology advancement, leakage power has become a significant source of total power consumption, and thus it is desirable to develop effective leakage-power reduction techniques for power optimization. The sensitivity-based technique has been shown to be an efficient approach to leakage power reduction by swapping gates (cells) with different threshold voltages. Nevertheless, its solution quality is limited and unstable because the technique does not have a global view on the effects of the gate swapping on other gates. To remedy this weakness, we develop a novel sensitivity formulation with a more global view on the gate-swapping effects. We also develop two static-timing-analysis engines embedded in the proposed algorithm to improve the efficiency. Experimental results show that our algorithm can effectively reduce leakage power by up to 74.4%. Compared with the state-of-the-art sensitivity-based method, we can achieve more leakage-power reduction by up to 20.6% and consume less running time and memory. The results show the effectiveness and efficiency of our algorithm.
12 Nov 2008
TL;DR: This chapter focuses on the representations for the packing structure, the most general floorplan representation which can model a floorplan with empty rooms, and the modelling, properties, and operations of the popular packing floorplan representations in the literature.
Abstract: As technology advances, design complexity is increasing and the circuit size is getting larger. To cope with the increasing design complexity, hierarchical design and IP modules are widely used. This trend makes module floorplanning/placement much more critical to the quality of a VLSI design than ever. A fundamental problem to floorplanning/placement lies in the representation of geometric relationship among modules. The representation profoundly affects the operations of modules and the complexity of a floorplan/placement design process. It is thus desired to develop an efficient, flexible, and effective representation of geometric relationship for floorplan/placement designs. Many floorplan representations have been proposed in the literature. We can represent a floorplan as a rectangular dissection of the floorplan region, and classify the representations based on the floorplan structures that the representations can model. Preceding chapters have covered the slicing structure [16,19] which can be obtained by repetitively subdividing rectangles horizontally or vertically into smaller rectangles, and the mosaic structure [4] for which the floorplan region is dissected into rooms so that each room contains exactly one module. The mosaic structure is more general than the slicing structure in the sense that the former can model more floorplan structures. This chapter focuses on the representations for the packing structure, the most general floorplan representation which can model a floorplan with empty rooms. There is a special type of the packing structure, the compacted structure, for which modules are compacted to some corner of the floorplan region, say the bottom-left corner, and no module can further be shifted down or left. The compacted structure induces much smaller solution spaces than the general one. Unlike the general packing representation which can fully model the topological relationship among modules [8, 9, 14, 15, 25], however, the compacted packing representations [1, 3, 12] can model only partial topological information, and thus the module dimensions are required in order to construct an exact floorplan. In this chapter, we shall detail the modelling, properties, and operations of the popular packing floorplan representations in the literature: compacted floorplan representations such as O-tree, B*-tree, and Corner Sequence (CS), and general packing ones such as Sequence Pair (SP) [14], Bounded Sliceline Grid (BSG), Transitive Closure Graph (TCG), Transitive Closure Graph with a Sequence (TCG-S), and Adjacent Constraint Graph (ACG) [25].
TL;DR: The results reveal the effectiveness of the X architecture on wirelength reduction during placement and, thus, the importance of the study on the X-placement algorithms, which is different from the results given in the work of Ono et al. which suggests thatthe X-architecture placement might not improve theX-routing wirelength over the Manhattan-arch Architecture placement.
Abstract: In this paper, we derive the X-half-perimeter wirelength (XHPWL) model for X-architecture placement and explore the effects of three different wire models on X-architecture placement, including the Manhattan-half-perimeter wirelength (MHPWL) model, the XHPWL model, and the X-Steiner wirelength (XStWL) model. For min-cut partitioning placement, we apply the XHPWL and XStWL models to the generalized net-weighting method that can exactly model the wirelength after partitioning by net weighting. For analytical placement, we smooth the XHPWL function using log-sum-exp functions to facilitate analytical placement. This paper shows that both the XHPWL and XStWL models can reduce the X wirelength effectively. In particular, our results reveal the effectiveness of the X architecture on wirelength reduction during placement and, thus, the importance of the study on the X-placement algorithms, which is different from the results given in the work of Ono et al. which suggests that the X-architecture placement might not improve the X-routing wirelength over the Manhattan-architecture placement.