Showing papers presented at "Asia Symposium on Quality Electronic Design in 2012"

Solar Harvested energy prediction algorithm for wireless sensors

Abstract: Recently, wireless sensing nodes are being integrated with ambient energy harvesting capability to overcome limited battery power budget constraint and extending effective operational time of sensor network. Solar panels are more frequently used to collect light energy for wireless sensing node. In order to efficiently utilize solar harvested energy in design, precise solar harvested energy prediction is a challenging task due to irregularity in solar energy patterens because of continually changing weather conditions. In this paper, we are presenting efficient algorithm for solar energy prediction based on additive decomposition (SEPAD) model. In this model, we are individually considering both seasonal and daily trends along with Sun's diurnal cycle. The performance of this algorithm is compared with existing solar energy prediction approaches and results show that our algorithm performance is better than existing approaches.

Wideband LNA design for SDR radio using balanced amplifier topology

Abstract: This paper presents the design and development of a wideband low noise amplifier (LNA) suitable for Software Defined Radio (SDR) base station. The LNA design is based on the balanced amplifier topology, using the hybrid coupler and advanced GaAs E-PHEMPT transistor technology in order to produce a good wideband performance on all the critical parameters. By using the balanced amplifier design topology, the design yields excellent return loss, noise figure and linearity performance for the wideband application, and by utilizing the hybrid coupler in the balanced amplifier topology reduces the PCB size compared to normal balanced amplifier topology. The wideband LNA was designed on a PCB board with FR4 substrate and exhibits a small signal gain of 18 dB, noise figure of 1 dB, return loss (input and output) greater than 10 dB and IIP3 greater than 11 dBm across the wideband frequency range from 136-941 MHz (TIA-603C full frequency range), with a dual supply of 5V and total current consumptions of 120mA.

3D IC implementation for MPSOC architectures: Mesh and butterfly based NoC

Abstract: In the CMOS technologies below 65 nm the wire delay dominates the gate delay. 3D IC design is one solution to deal with this problem. We propose in this work to implement two different MPSOC architectures based on Mesh and Butterfly NoC topologies. We use the 3D IC technology from the Tezzaron Company. Thanks to its symmetry, the mesh based NoC architecture is easier to implement compared to the other one based on the Butterfly NoC. In fact with this one, we have to deal with additional problems like mapping and partitioning. With its long links, the Butterfly architecture is a better example than the mesh topology to prove the efficiency of 3D design.

Signaling analysis of inter-chip I/O package routing for Multi-Chip Package

Abstract: Multi-Chip Package (MCP) is becoming a customary form of integration in many high performance and advanced electronic devices. The vast adoptions of this technology are mainly contributed by advantages for instance lower power consumption, heterogeneous integration of multiple silicon process technologies and manufacturers, shorter time-to-market and lower costs [1]. However, the high density interchip I/O routing within package presents unique signaling challenges when coupled with high operating data rate. This paper focuses on the signaling analysis of the inter-chip I/O package routing between silicon devices in MCP. In this study, high level signal quality and eye margin sensitivity were evaluated from 2.5GHz up-to 7.5GHz. The microwave effect is found dominating the transmission line component that resulted in signal quality deteriorations. Key limiting factors such as crosstalk coupling effects, signal reflections and frequency dependent losses that caused signal quality degradations were identified and categorized according to the operating frequency and channel length for future MCP design considerations.

Effects of hydroquinone and gelatin on the electrodeposition of SnBi low temperature Pb-free solder

Abstract: The effects of an antioxidant, hydroquinone (HQ) and a grain refining additive, gelatin, on the electroplating characteristics of SnBi alloys were investigated. Methane sulfonic acid (MSA) based plating baths with varying contents of additives are prepared and the electrochemical behavior of each bath was investigated. Cathodic polarization studies showed that the presence of HQ possesses insignificant effect on the deposition behavior. The combination of HQ and gelatin successfully reduces the deposition potential gap of both elements hence allows co-deposition of SnBi in this plating bath. The adhesion of deposits and the formation of spongy deposits are respectively improved and eliminated by the synergistic effects of these two additives. The electroplated SnBi deposits showed a decrease in Bi content and with increasing current density. Near eutectic Sn-60.75 wt.%Bi alloy was successfully deposited from the bath with both HQ and gelatin at a current density of 18 mA cm−2.

A bias-driven approach to improve the efficiency of automatic design optimization for CMOS OP-Amps

Abstract: The equation-based analog design automation is getting popular in last decade to search the optimal solutions with good efficiency. However, due to the deep-submicron effects, significant modeling errors often exist in major transistor parameters like g ds and g m . This often results in wrong prediction of circuit performance and leads to several redesign cycles to meet the specifications. Instead of building complex parameter models for g ds and g m , this paper adopts the g m /I d design concept, which is an independent value to the device size, on equation-based optimization to solve the accuracy issue. Without the complex effects from W and L, the modeling accuracy of transistor parameters is significantly improved. No more iteration is required by using the proposed approach, which improves the efficiency as well as the accuracy. To the best of our knowledge, this is the first work that adopts the internal voltages instead of device sizes as the unknown variables to be solved. As demonstrated on several circuits with different objectives, both the accuracy and efficiency of circuit optimization can be improved significantly.

Maximization of SRAM energy efficiency utilizing MTCMOS technology

Abstract: Higher-V th devices in the cross-coupled latches and the write access transistors, and lower-V th devices in the read ports are preferred for reducing leakage current without sacrificing performance. However, at ultra-low supply voltage levels, higher-V th devices can retard or nullify energy efficiency due to substantially slower write speed than read. This paper presents energy efficiency maximization techniques for 8T SRAMs utilizing multi-threshold CMOS (MTCMOS) technology and various design techniques. Simulation results using a commercial 65 nm technology show that the SRAM energy efficiency can improved up to 33× through MTCMOS and prior power reduction and performance boosting techniques.

A low-cost capacitive relative humidity sensor for food moisture monitoring application

Abstract: In this paper, a low-cost capacitive relative humidity hygrometer suitable for food moisture monitoring is presented. The variation of dielectric constant of polyimide film to relative humidity enables the sensor's functionality. A fully differential capacitance to digital converter is utilized as the hygrometer digital readout, which is immune to circuit wiring parasitic and enable the sensor's long-term stability. The humidity sensor is implemented using TSMC1P6M 0.18µm technology with thick top metal option. Simulation results indicate that an inaccuracy of +6/−5%RH can be achieved sensing from 10%RH ∼ 90%RH, with 5.4µW power consumption for sensing and 21.6mW power consumption for sensor heating.

Design of a wave-pipelined serializer-deserializer with an asynchronous protocol for high speed interfaces

Abstract: In this paper, we proposed an asynchronous wave-pipelined Serializer and Deserializer, or WP-SERDES in brief, that is totally clock-free. In contrast to conventional SERDES that employ power hungry phase-locked loops (PLLs) for synchronization in serializers and clock-data recovery (CDR) circuits in deserializers, the proposed WP-SERDES employs delay elements (DEs) consisting of inverter chains for timing reference. Besides, throughput of the proposed WP-SERDES is adjustable thanks to the voltage-controlled inverters used in the DEs. The proposed WP-SERDES which was simulated using 180nm CMOS process shows a 3.9 Gb/s throughput and 2.44 mW power consumption.

Effects of Mn nanoparticles on wettability and intermetallic compounds in between Sn-3.8Ag-0.7Cu and Cu substrate during multiple reflow

Abstract: In this research, the effects of Mn nanoparticles on wettability and interfacial intermetallic compounds in between Sn-3.8Ag-0.7Cu (SAC) solder and copper (Cu) substrate was investigated. The nanocomposite solders were fabricated by mechanical mixing of SAC solder paste with Mn nanoparticles. The melting characteristic of the solders was characterized by differential scanning calorimeter (DSC). The solder pastes were reflowed in a reflow oven at 250°C for 60 seconds. The spreading rate and contact angle of the solders was calculated to measure the wettability. The solder joints were characterized by field emission scanning electron microscope (FESEM) and energy dispersive X-Ray (EDX). It was found that with the addition of Mn nanoparticles the total IMC thickness decreased after first and six times reflow. The Cu 3 Sn layer was not affected with the addition of Mn nanoparticles. However, some probable mechanism is suggested to explain the effect of Mn nanoparticles on SAC solder.

Unified model for analyzing timing delay and crosstalk effects in Carbon Nanotube interconnects

Abstract: Carbon Nanotube (CNT) has become the promising candidate for replacing the traditional Copper (Cu) based interconnect systems in future technology nodes. This paper presents an analytical model for timing and crosstalk in the CNT based nano-interconnect systems. The proposed model is compared with SPICE and it is found that the proposed model is 100% accurate with respect to SPICE and in an average ∼250 times faster than SPICE. Using the proposed analytical model the crosstalk noise, delay, overshoot/undershoot are estimated in CNT based nano-interconnects for three different CNT parameters; CNT diameter, length, and metallic fraction.

A methodology for LBIST logic diagnosis in high volume manufacturing

Abstract: LBIST (Logic Built-In Self Test) is a structural test method that tests a circuit by running test patterns generated on the die as opposed to ATPG (Automatic Test Pattern Generation) method in which the test patterns are pre-generated to test specific fault types LBIST has emerged as an alternative scan based test methodology due to its attractive benefits such as reduced pattern size and field testability LBIST uses pseudo random patterns enabling it to generate patterns on the die saving tester memory to a large extent At the same time it poses challenges to enable fail data collection for later debug as the LBIST test iterations are usually large (typically 100000) Tester time is not a big concern for a LBIST based method if the objective is to know if the unit passed or failed, but memory usage is a concern due to the need to compare intermediate scan responses to determine and collect failing responses for diagnosis and debug purposes This motivated us to come up with a methodology for fail data collection that optimizes tester time and memory and collects enough fail data to provide acceptable diagnosis quality In this paper we have presented a methodology for fail data collection and discussed the tester overheads for LBIST logic diagnosis

Analysis of system bus on SoC platform using TSV interconnection

Abstract: This paper proposes a latency model for a multi-layer system on chip (SoC) structure employing through silicon vias (TSVs). TSVs are used to interconnect multiple SoC chips stacked to form a three-dimensional (3-D) structure. The proposed latency model has been used to estimate the system performance. The performance estimation reflects the number of IPs connected to the system bus, data throughput and the number of masters in the system. The maximum throughput calculation results can be used to find the appropriate number of chips to be stacked during the 3-D multi-layer SoC system design process.

A 2.5–12.5Gbps interpolator-based clock and data recovery circuit for FPGA

Abstract: This paper presents a programmable half-rate clock and data recovery (CDR) circuit for plesiochronous serial I/O links. The CDR is implemented in TSMC 28nm high-k metal-gate CMOS technology and covers a continuous range of data rates from 2.5Gb/s to 12.5Gb/s. The higher data rate is achieved by demultiplexing and decimating the sampled data in order for the subsequent circuit to operate at a much lower speed. The CDR is able to track maximum frequency deviation of ±286.78 ppm between the incoming data and the local reference clock at 12.5Gb/s. The CDR occupies a chip area of 18700um2 and consumes 30.30mW of power at 12.5Gb/s.

Retention time characterization and optimization of logic-compatible embedded DRAM cells

Abstract: Logic-compatible 2T and 3T embedded DRAMs (eDRAM) have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in eDRAM cells are cell area, data retention time and read speed. In this paper, we present an in-depth analysis on the data retention time of various logic-compatible eDRAM cells, followed by the effects of several design factors on the retention time. A systematic methodology is proposed for enhancing the retention time of the eDRAM cells. Simulation results using a standard 65nm CMOS technology show that the optimization process improves the data retention time more than 3×. Finally, the number of read operations per retention period is estimated to show the effectiveness of each eDRAM cell. Analysis demonstrates that although the 2T eDRAM cell has a shorter retention time than the conventional 3T cell, it has better effectiveness due to the faster read operation.

Simultaneous switching noise impact to signal eye diagram on high-speed I/O

Abstract: Simultaneous Switching Noise (SSN) is increasing with higher I/O data rate, resulting into more challenges in regulating supply voltage noise. SSN increases jitter in high-speed interface circuit and limits the performance of I/O. In order to reduce SSN effect to supply voltage droop, Power Distribution Network (PDN) has to be designed optimally. PDN design goal is to reduce the power supply noise going into I/O circuit. Engineering efforts are focused on packaging and board routing in order to control the impedance profile and supply voltage droop within the design specification. This paper discusses the next level of investigation, quantifying the effect of supply noise to the I/O transistor level circuit performance, specifically on Universal Serial Bus (USB) transmitter circuit. Output of the USB's transmitted signal is shown in eye diagram with the existence of supply noise throughout PDN. Results show that the USB transmitter circuit can sustain with higher supply noise drop than the targeted PDN design.

Robustness validation of integrated circuits and systems

Abstract: Robust system design is becoming increasingly important, because of the ongoing miniaturization of integrated circuits, the increasing effects of aging mechanisms, and the effects of parasitic elements, both intrinsic and external. For safety reasons, particular emphasis is placed on robust system design in the automotive and aerospace sectors. Until now, the term robustness has been applied very intuitively and there has been no proper way to actually measure robustness. However, the complexity of contemporary systems makes it difficult to fulfill tight specifications. For this reason, robustness must be integrated into a partially automated design flow. In this paper, a new approach to robustness modeling is presented, in addition to new ways to quantify or assess the robustness of a design. To demonstrate the flexibility of the proposed approach, it is adapted and applied to several different scenarios. These include the robustness evaluation of digital circuits under aging effects, such as NBTI; the robustness modeling of analog and mixed signal circuits using affine arithmetic; and the robustness study of software algorithms on a high system level.

Field-based parasitic capacitance models for 2D and 3D sub-45-nm interconnect

Abstract: In the design of scaling complementary metal-oxide-semiconductor (CMOS), back-end-of-the-line (BEOL) interconnection becomes a limiting factor to circuit performance. Compact models for paratactic capacitance, which are scalable with wire geometries, are desired for circuit simulation and design. Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. The solution can be easily extended to the case of two parallel wires. Its physical base minimizes the complexity and error comparing with a traditional model fitting process. The new compact model has been verified with COMSOL simulations. It accurately predicts the capacitance for not only the nominal wire dimensions from the latest ITRS updates, but also for a wide range of other BEOL wire dimensions.

Effects of thiourea and gelatin on the electrodeposition of Sn-Ag solder alloy

Abstract: Sulfuric acid based Sn-Ag plating baths were developed to study the individual as well as synergistic effects of thiourea (TU) and gelatin on the characteristics of Sn-Ag deposits. Electrochemical behavior of each bath was investigated by cathodic polarization studies. Results showed that the deposition potential gap of both elements was reduced by both additives, hence allowing co-deposition of Sn-Ag to occur. In this study, TU increases Ag composition and changes deposits microstructure. Low content of gelatin inhibits Ag deposition but high content of gelatin results in enhanced Ag deposition. Microstructure of deposits has been improved by the synergistic effects of these two additives. Near-eutectic composition of Sn-4.0 wt.% Ag is achieved with the aid of 2g/L of TU and 1g/L of gelatin at a current density of 10mA cm−2.

Clock tree construction using gated clock cloning

Abstract: Clock gating is one of the important techniques to achieve low power and small area in high-performance synchronous circuit design. In this paper, we propose a three-phase clock gating optimization methodology by using clustering and merging algorithm to construct a gated clock tree with minimal number of clock gating cells and buffers. In addition, according to the fan-out numbers of a clock gating cell, we derive a parameter γ that may be used to adjust the tradeoff between clock gating cell and buffer. The experimental results show that the number of clock gating cells and buffers reduced in each phase in our algorithm. Our solutions are better than greedy approach.

A monotonic and low-power digitally controlled oscillator using standard cells for SoC applications

Abstract: In this paper, a monotonic and low-power digitally controlled oscillator (DCO) with cell-based design for System-On-Chip (SoC) applications is presented. The proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Besides, based on the proposed two-level controlled interpolation structure, the proposed DCO can provide monotonic delay with low power consumption and low circuit complexity as compared with conventional approaches. Simulation results show that power consumption of the proposed DCO can be improved to 0.337mW (@1118MHz) with 0.82ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.

A new design methodology of networks on chip

Abstract: The paper proposes an FPGA-like approach to on-chip communication and comes up with a design methodology where switches are avoided and where two any IPs are connected if and only if they are communicating. It avoids the problem of costly (time, area, energy) intermediate hop counts of on-chip networks (NOCs) between any two source-destination pairs. The second novelty is that without knowing the overlap/disjointness of communication packets between any two IP blocks, a designer may use unnecessary resources (wasting time, space, energy, resources, etc). So, we look into the temporal aspect of communication and then it is possible that some communication phases don't overlap, thus a designer needs not provision resources for such cases. Based on this methodology, our CAD tool aims at designing NOCs subject to bandwidth, area and energy constraints.

The effect of higher order model decoupling capacitors in the design of a power delivery network

Abstract: Decoupling capacitors are widely used in power delivery network (PDN) design to mitigate switching noise from the integrated circuit (IC). Besides, they also provide a low-impedance path to shunt the transient energy to ground at the IC source. Since a real capacitor includes both parasitic inductance and resistance associated with the interconnection and package of the capacitor resulting in an increase in impedance, adequate decoupling capacitances in a PDN design are essential. Often, a capacitor is represented with a higher order model (HOM) of resistance, inductance and capacitance in power delivery simulation. This paper presents the findings from an investigation into the PDN performance using various HOM decoupling capacitors of the same capacitance. The reasons for the different HOM values with the same capacitance include the form factor, manufacturing processes and the operating temperature of the capacitors. From the study, it was found that both the form factor and the differences in the capacitors manufacturing process can cause a significant difference in the impedance profile as well as the voltage droop whereas the operating temperature has a much less impact on the PDN performance.

Load model technique for mesh-structured power distribution network

Abstract: This paper proposes an efficient load model for power network noise analysis. The proposed method approximates an uninteresting part of a large mesh-structured circuit to a simple load model which consists of a couple of RLC elements. In the experimental results, the proposed method reduced a CPU time of SPICE simulation by up to 95% while suppressing the maximum and average voltage errors less than 0.0207 V (1.4%) and 0.0048 V (0.325%) respectively.

Phosphor concentration effects on the thermal and optical performance of cool and warm white single chip LEDs

Abstract: Phosphor converted light emitting diodes (LEDs) are emerging are the most promising solid state lighting source since the past few decades and with no doubt in few years to come, this technology would conveniently replace the current lighting industries. This paper elucidates the significance of thermal and optical performance difference between cool and warm white LEDs. The analyses were carried out in terms of effects of phosphor concentration on the rise in junction temperature, thermal resistance as well as the optical properties of the samples. It was observed that the cool white samples achieved 6.68% less junction temperature compared to warm white LED recorded at room temperature of 25.1°C and the average efficiency of the cool white LED was found to be higher in magnitude compared to warm white LEDs. The effects of phosphor concentration on degradation of LED performances were discussed in terms of photon scattering, light trapping and thermal loading phenomena.

Thermal and optical analysis of multi-chip LED packages with different electrical connection and driving current

Abstract: The junction temperature and the thermal resistance are vital characteristics that will determine the overall performance of LED packages. The influence of two different electrical connections of multi-chip LED packages on the thermal and optical characteristics is discussed in this paper. The thermal and optical characteristics of the LED package are investigated. Measurements are carried out on LED packages with series and parallel connections in sequence. The objective of this study is to compare the thermal and optical performance of the LED packages with different electrical connections. Experimental results revealed that there is a slight variation of 3 to 5% in R thJA and ΔT J values between both connections. For both thermal and optical measurements, the results for parallel connection are observed to be better than that for series connection.

A robust incremental power grid analyzer by macromodeling approach and Orthogonal Matching Pursuit

Abstract: As VLSI techniques are getting more and more advanced, the size of the power grid network increases dramatically. Therefore, the power grid analysis becomes a challenging task during the design procedure. This work utilizes the macromodeling technique [1] and enhances the Orthogonal Matching Pursuit (OMP) based method [2] to develop an effective and robust incremental analysis method for the power grid network, MA-OMPt. Given a power grid network, MA-OMPt not only can deal with the change of its element values but also can handle the modification of its topology. The experimental results show that MA-OMPt can be an order of magnitude faster than the OMP-based method [2] which can only deal with the change of element values of the power grid. The experimental results also demonstrate that MA-OMPt can accurately and efficiently handle the modified topology of the power grid network.

Genetic algorithm-based optimization in 4th order Sallen Key high pass filter

Abstract: Circuit designers often face difficulties and challenges to deal with the complex trade-offs of Analog IC design. Considering such complex trade-offs, optimization of circuit design often requires large amount of time and effort. This paper proposed a Genetic Algorithm (GA)-based optimization model for optimizing the design variables of a 4th order Sallen Key high pass filter. The aims of the design are to maximize the output gain, minimize the pass-band ripple, and achieve the targeted cut-off frequency. The GA is executed in conjunction with the LTSPICE circuit simulation system to assess the filter performance. Overall results satisfied the required design specifications.

0.5 V, 3 6µW G m -C Butterworth low pass filter in 0.18µm CMOS process

Abstract: This paper presents a low voltage, low power continuous-time (G m -C) 4th order low pass Butterworth filter with a 3-dB bandwidth of 1MHz and capable of operating at supply voltage as low as 0.5V in 0.18 µm. The filter uses bulk-driven technique for achieving the necessary head-room. The simulation results show that the filter has a peak-to-peak signal swing of 1.2V (differential) for 1% THD and a dynamic range of 54 dB. The power consumed by the filter is 36µW when operating at a voltage of 0.5 V. The Figure of Merit (FOM) achieved by the filter is 0.05 fJ and is found to be lowest among the similar filters found in the literature.

On regularity and integrated DFM metrics

Abstract: Transistor geometries are well into the nanometer regime, keeping with Moore's Law. With this scaling in geometry, problems not significant in the larger geometries have come to the fore. These problems, collectively termed variability, stem from second-order effects due to the small geometries themselves and engineering limitations in creating the small geometries. The engineering obstacles have a few solutions which are yet to be widely adopted due to cost limitations in deploying them. Addressing and mitigating variability due to second-order effects comes largely under the purview of device engineers and to a smaller extent, design practices. Passive layout measures that ease these manufacturing limitations by regularizing the different layout pitches have been explored in the past. However, the question of the best design practice to combat systematic variations is still open. In this work we explore considerations for the regular layout of the exclusive-OR gate, the half-adder and full-adder cells implemented with varying degrees of regularity. Tradeoffs like complete interconnect unidirectionality, and the inevitable introduction of vias are qualitatively analyzed and some factors affecting the analysis are presented. Finally, results from the Calibre Critical Feature Analysis (CFA) of the cells are used to evaluate the qualitative analysis.