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Southern Conference Programmable Logic 

About: Southern Conference Programmable Logic is an academic conference. The conference publishes majorly in the area(s): Field-programmable gate array & Reconfigurable computing. Over the lifetime, 263 publication(s) have been published by the conference receiving 1670 citation(s).
Papers published on a yearly basis
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Proceedings ArticleDOI
01 Apr 2009
TL;DR: The Cube, a massively-parallel FPGA-based platform is presented, which can perform a full search on the 40-bit key space within 3 minutes, this being 359 times faster than a multi-threaded software implementation running on a 2.5GHz Intel Quad-Core Xeon processor.
Abstract: Cube, a massively-parallel FPGA-based platform is presented. The machine is made from boards each containing 64 FPGA devices and eight boards can be connected in a cube structure for a total of 512 FPGA devices. With high bandwidth systolic inter-FPGA communication and a flexible programming scheme, the result is a low power, high density and scalable supercomputing machine suitable for various large scale parallel applications. A RC4 key search engine was built as an demonstration application. In a fully implemented Cube, the engine can perform a full search on the 40-bit key space within 3 minutes, this being 359 times faster than a multi-threaded software implementation running on a 2.5GHz Intel Quad-Core Xeon processor.

58 citations


Proceedings ArticleDOI
18 Jun 2007
TL;DR: An 64-bit FPGA implementation of the 128- bit block and 128 bit-key AES cipher, designed by Joan Daemen and Vincent Rijmen, and operating at 224 Mbps (maximum throughput).
Abstract: The Rijndael cipher, designed by Joan Daemen and Vincent Rijmen, has been selected as the official advanced encryption standard (AES) and it is well suited for hardware use. This implementation can be carried out through several trade-offs between area and speed. This paper presents an 64-bit FPGA implementation of the 128- bit block and 128 bit-key AES cipher. Selected FPGA Family is Spartan 3. The cipher consumes 52 clock cycles for algorithm encryption, resulting in a throughput of 120 Mbps. Synthesis results in the use of 1643 slices, 975 flip flops, 3055 4-input look up tables and operates at 224 Mbps (maximum throughput). The design target was optimization of speed and cost.

44 citations


Proceedings ArticleDOI
18 Jun 2007
TL;DR: A reconfigurable platform for sensor networks is presented that has features that allow easy reuse of the node in several applications avoiding redesigning the system from scratch.
Abstract: A reconfigurable platform for sensor networks is presented. This platform has features that allow easy reuse of the node in several applications avoiding redesigning the system from scratch. The node includes an FPGA which is the core of the reconfiguration capabilities of the node. Several hardware interfaces for sensor standard protocols like I2C or PWM have been developed and implemented in the FPGA. Remote reconfiguration is an important feature and sensor networks can take advantage of it in order to improve the global performance.

40 citations


Proceedings ArticleDOI
20 Mar 2012
TL;DR: In this article, convolution was implemented in each of the aforementioned architectures with the following languages: CUDA for GPUs and Verilog for FPGAs, and the same algorithms were also implemented in MATLAB, using predefined operations and in C using a regular x86 quad-core processor.
Abstract: Convolution is one of the most important operators used in image processing. With the constant need to increase the performance in high-end applications and the rise and popularity of parallel architectures, such as GPUs and the ones implemented in FPGAs, comes the necessity to compare these architectures in order to determine which of them performs better and in what scenario. In this article, convolution was implemented in each of the aforementioned architectures with the following languages: CUDA for GPUs and Verilog for FPGAs. In addition, the same algorithms were also implemented in MATLAB, using predefined operations and in C using a regular x86 quad-core processor. Comparative performance measures, considering the execution time and the clock ratio, were taken and commented in the paper. Overall, it was possible to achieve a CUDA speedup of roughly 200× in comparison to C, 70× in comparison to Matlab and 20× in comparison to FPGA.

35 citations


Proceedings ArticleDOI
01 Apr 2009
TL;DR: A low cost FPGA based solution for a real-time moving object tracking system based on a soft RISC processor capable of running kernel based mean shift tracking algorithm within the required time constraint is presented.
Abstract: This paper presents a low cost FPGA based solution for a real-time moving object tracking system. A specialized architecture is presented based on a soft RISC processor capable of running kernel based mean shift tracking algorithm. The system includes a frame grabber unit that stores the video frame in DDR RAM using direct memory access, a video display unit to monitor the tracking statistics and a soft processor capable of running mean shift tracking algorithm within the required time constraint.

35 citations


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Performance
Metrics
No. of papers from the Conference in previous years
YearPapers
201916
201422
201242
201146
200938
200853