Showing papers presented at "Symposium on VLSI Technology in 1986"

0.5 Micron Gate CMOS Technology Using E-Beam/Optical Mix Lithography

Abstract: A high performance CMOS process using mix e-beam/optical lithography has been developed for VLSI applications. The 0.5 ?m channel devices are fabricated with shallow N+ and P+ source/drain junctions. Self-aligned silicide on gate and diffusions reduces the sheet resistance to 5 ohm/sq.. The shallow retrograde N-well formed by multiple high energy phosphorous implants without a drive-in a allows the use of thin P/P+ epi for latch-up control.

A Simple Holding Voltage Analysis for Latchup in Epitaxial CMOS

Abstract: This paper presents a simple model for the holding voltage of the parasitic thyristor in epitaxial n-well CMOS. Two-dimensional device simulations of the holding point show that the region between the p+ source and the n+ source is conductivity modulated. The vertical extension of the conductivity modulated region is often greater than the tank depth. Conductivity modulation causes these regions of the p-epi and n-well to lose their separate identities. As a result the vertical hole current in both the p-epi and n-well is well represented by the majority carrier flow equations for a single transistor in high current operation. The lateral current flow is drift dominated. An expression for the holding voltage is derived based on this simplification. The analysis explains the improvement in holding voltage with increased n-to-p spacing, thinner epi, substrate backbias, shallow trench and silicided source/drain.

A Novel CMOS Process Utilizing After-Gate-Implantation Process

Abstract: The CMOSprocesssequenceusingtheAGIprocess is shown in Fig.1. (a)Isolationregionsand polysilicon gatesare formed.Thewell contact regioniscoveredby thegate.(b)The PMOS area is masked.P-well implantationand channel implantation throughtte isolation oxideandthe gatepolysilicon, andn -source/drain implantation areperformedsuccessively. (c)TheNMOS areais masked.Channelimplantation throughtheisolati+n oxide and the gate polysilicon,and p source/drainimplantationare performed successively. (d)Thepolysilicon over thewellcontast regionisselectively etched,afterwhich thep -layerisimplanted. (e)Contactwindowsare opened,followed by themetallization process. ThisCMOS processrequiresonly 7 masks,in comparison with10masksneededina conventional CMOS process (1).If well contacts are not necessaryin sucha deviceas SOI CMOS,only6 masksarerequired.

Oxide Defect Density, Failue Rate and Screen Yield

Abstract: The concepts of "weakness factor", w, and defect density, D(w), are introduced for thin oxide study. The defect density is sensitive to silicon material qualities and process conditions and can be characterized by simple time-to-breakdown or ramp-breakdown field measurements (see Figure 1). We present an experimentally verified method of predicting the time-dependent dielectric breakdown (TDDB) behavior for different oxide area and field using D(w). We also demonstrate a method for determining the stress time and stress field required for screening to meet a given failure rate for any oxide area and operating field, and the yield loss due to screening. Based on this study, there appears to be a large window between adequate screen and over-screen.

Submicron 3D Surface-Orientation-Optimized CMOS Technology

Abstract: INTIODUCTION For achieving high performance VLSI's in logic and memory applications, CMOS becomes the dominant technology due to its high speed operation and low power dissipation. However, since (100) wafer is used from a view point of NMOSFET's characteristics, conventional planar technologies give rise to loss of balance between electron and hole mobility. This unbalance results in large PMOS device size for designing optimum circuits, which naturally increases parasitic capacitances such as junction capacitance and gate capacitance. As a result, obtained CMOS operation speed is lower than expected. (110) Si surface is thus more preferable for PMOSFET's due to the highest hole mobility. However, it degrades NMOS reliability, which is highest on (100) surface orientation [1]. Therefore, it is most desirable to utilize optimum Si surface orientation for NMOSFET's and PMOSFET's individually on the same substrate. In this paper, a 3-dimensional CMOS (3D CMOS) structure has been proposed. In this structure, PMOSFET's are fabricated on a (110) surface obtained by a trench sidewall formed on a (100) Si substrate, while NMOSFET's are fabricated on the (100) substrate as usual. Therefore, the highest hole mobility is obtained for PMOSFET's, maintaining high NMOS reliability. Based upon this technology, the 3D CMOS was fabricated and its device performance was characterized.

Quantum Semiconductor Devices

Abstract: The construction of a quantum electronics technology will involve a concentrated effort in basic device physics, advanced fabrication, and novel architectures. The basic physics on which devices in this technology will probably operate are quantum size effects and quantum mechanical tunneling, considerably different from conventional devices. Structures which exhibit these effects have been demonstrated. The realization of the basic devices in this technology is underway. The prototype architectures in this technology must exploit strong local device coupling, and are known as "cellular automata". The need of such architectures is driven by the need to eliminate interconnects, and is natural for "quantum-coupled devices". This revolutionary approach in both device and architecture is inherent in the desire to scale far beyond present VSLI.

Two-Dimensional Simulation of Glass Reflow and Silicon Oxidation

Abstract: A general-purpose program for the two-dimensional (2D) simulation of processes with moving boundaries has been written. The program is capable of simulating the growth or deformation of regions for problems with almost any arbitrarily shaped initial geometry. In this paper. we describe the application to the problems of glass reflow as well as local oxidation. Aside from predicting final profiles. it can also calculate the stress generated within the media and at the interfaces. The latter capabilitv is particularlv important for optimizing oxidation technology while avoiding defects in the silicon substrate caused bv high stress levels.

Asymmetry of the Substrate Current Characteristics Enhanced by the Gate Bird's Beak

Abstract: INTRODUCTION Lightly doped drain (LDD) structure has recieved much attention as an important VLSI device. Especially its substrate current characteristics and the device degradation mechanism have been intensively studied(1,2). It has been, however, reported that there exists the asymmetry of the transistor characteristics in LDD MOSFETs. This asymmetry is caused by the shadowing of ion beams by the gate electrode, and enhanced by the gate bird's beak, which is introduced by the reoxidation after the source/ drain implantation. This asymmetry also influences the hot carrier generation (3,4). In this paper, the substrate current characteristics of the asymmetrical LDD MOSFET have been investigated. It has been found that the substrate current versus gate voltage characteristics have a double hump or a long tail instead of the usual single peak, and that these effects are caused by the asymmetry of n-impurity profile and the gate bird's beak.

Self-Aligned Refresh Scheme for VLSI Intelligent Dynamic RAMs

Abstract: 1. Int-oduction Recently. intelligent dynarnic RAMs have been proposed to ease a cumbersome refresh timing control and to enable a battery back-up operation. Among them are a self-refresh dynamic RAM. a pseudo SRAM (PSRAM)') and a virtually SRAM (VSRAM)2). The last one completely frees the users from the refresh operation. The key circuit technology in making these intelligent DRAMs is a construction of a refresh timer, which tells the time when a refresh operation is needed. Conventionally, a ring oscillator has been used for this refresh timer. However, the voltage, temperature, and process dependencies of the ring oscillation frequency are far from being optimized. Therefore, one or two orders of magnitude higher refresh frequency is to be chosen to keep a margm, resulting in a high standby current of the RAM. A self-aligned refresh scheme, namely a leak sensor, is newly proposed in this paper to fully overcome this problem. Since the leak sensor determines the refresh intervals in a self-aligned way with the memory cell charge leakage, it offers the optimized refresh frequency. Novel preset scheme cancels the circuit instabilities caused by the process fluctuations. Leakage characteristics of a capacitor is also investigated in relation to the leak sensor. The effectiveness of the leak sensor is demonstrated by a lMbit VSRAM.

The Impact of Non-Ohmic Polysilicon Emitter Resistance on Bipolar Transistor Performance

Abstract: The potential performance enhancement of polysilicon emitters in bipolar transistors may be reduced when the contact resistance is high and nonohmic. Our experimental data shows the expected correlation between DC series resistance and AC switching performance even for polysilicon emitters without intentional interface oxides.

An Analytical Perspective of LDD MOSFETs

Abstract: The quasi-two-dimensional approach has been used to develop a simple electric-field model for LDD MOSFETs. This paper presents an analytical perspective of the field distribution, cause of the double-peak characteristics of Isub, synthesis of LDD doping profile, effect of source/drain offset, and the short channel effect in LDD devices. This perspective supplements the experimental studies and computer simulations of LDD structures.

Simultaneous Formation of TiN and TiSi2 by Rapid Lamp Annealing in NH3 Ambient for VLSI Contacts

Abstract: The bilayer of self-aligned TiN/TiSi2 was formed by the lamp annealing in N2 or NH3, simultaneously. Thickness ratio TiN/TiSi was able to be controled by the condition of annealing temperature and/or annealing ambient (N2, NH3); by the annealing in NH3 at lower temperature, the relatively thicker TiN layer was formed. Chemical stability and the electrical characteristics of the AlSi/TiN/TiSi2/n+Si contact system were studied. It was found that the bilayer of TiN/TiSi2 formed by the lamp annealing had good chemical stability in HF, low contact resistance to n+Si, and the good barrier effect on Al diffusion.

Epitaxial SiC Emitter for High Speed Bipolar VLSIs

Abstract: Introduction For future high speed bipolar VLSIs besides reduced transistor size, desirable improvement is a transistor with a wide-gap emitter. The principal benefit is the major reduction in the base resistance because emitter efficiency, i.e. the current gain is not directry dependent on the base doping, which may be very high. But little technology existed to form an excellent junction between a wide-gap emitter and a Si base. We have recently developed a growth technique for cubic SiC (Eg=2.2 eV) epitaxial film on Si substrate at 1000C, which is lower than previously reported.1) This paper discusses the possibility of using the material as a wide-gap emitter.

The Impact of Intrinsic Series Resistance on MOSFET Scaling

Abstract: The intrinsic parasitic series resistance associated with the practical structure of a MOSFET is examined. The components considered include contact resistance, diffusion sheet resistance, spreading (injection) resistance, and accumulation layer resistance. The impact of the total resistance on MOSFET scaling is assessed, down to a channel length of 0.15 µm. The results show that, contrary to what has been claimed before, the transconductance and current of a MOSFET continue to increase as the channel length is miniaturized, although the degradation percentage-wise compared to an ideal device without series resistance continues to increase. Based on the degraded I-V characteristics and their effects on an inverter, it is shown here that for NMOS or PMOS digital circuits, the maximum degradation in speed due to series resistance is 20-35 percent compared to ideal scaling for the shortest channel considered. For CMOS circuits, the maximum degradation is reduced to 7-15 percent. In absolute terms, a loss of speed in either case due to miniaturization of channel length is not expected even down to 0.15 µm.

Speed Enhancements and Key Design Aspects of Charge Buffered Logic

Abstract: Recently a new bipolar complementary transistor logic called Charge Buffered Logic (CBL) has been proposed('. This unique circuit concept features large dynamic currents for switching, but requires very low DC currents of a few microamps in the quiescent state, thus significantly reducing the average power dissipation similar to CMOS. As a drawback of the early experimental result, the speed has been considerably limited by the low cut-off frequency fT of the PNP transistor.

Comparison of TiSi2 and WSI2 Silicided Shallow Junctions for Sub-Micron CMOSs

Abstract: INTRODUCTION With the decrease of the junction depth of sub-micron CMOS devices, the development of lowresistivity shallow junctions is much needed. Selfaligned silicided source and drain (S/D) are most promising technology to meet the demand (1,2,3). In this report, the silicided shallow junctions using titanium disilicide (TiSi ) and tungsten disilicide (WSi2) are compared in terms of the manufacturing processes and the device characteristics of sub-micron CMOSs. The diffusion from implanted silicides is discussed, which can form heavily doped shallow junctions. Moreover, submicron CMOSs with TiSi2 and WSi2 silicided S/D have been successfully fabricated with LDD structures.