Showing papers by "Cadence Design Systems published in 2012"

Plasma and Cerebrospinal Fluid Pharmacokinetic Parameters after Single-Dose Administration of Intravenous, Oral or Rectal Acetaminophen

Abstract: Background: This is the first study to compare plasma and cerebrospinal fluid (CSF) pharmacokinetics of intravenous (IV), oral (PO), or rectal (PR) formulations of acetaminophen. Methods: Healthy male subjects (N = 6) were randomized to receive a single dose of IV (OFIRMEV®; Cadence) 1,000 mg (15 minute infusion), PO (2 Tylenol® 500 mg caplets; McNeil Consumer Healthcare), or PR acetaminophen (2 Feverall® 650 mg suppositories; Actavis) with a 1-day washout period between doses. The 1,300 mg PR concentrations were standardized to 1,000 mg. Acetaminophen plasma and CSF levels were obtained at T0, 0.25, 0.5, 0.75, 1, 2, 3, 4, and 6 hours. Results: IV acetaminophen showed earlier and higher plasma and CSF levels compared with PO or PR administration. CSF bioavailability over 6 hours (AUC0–6) for IV, PO, and PR 1 g was 24.9, 14.2, and 10.3 μg·h/mL, respectively. No treatment-related adverse events were reported. One subject was replaced because of premature failure of his lumbar spinal catheter. The mean CSF level in the IV group was similar to plasma from 3 to 4 hours and higher from 4 hours on. Absorption phase, variability in plasma, and CSF were greater in PO and PR groups than variability with IV administration. Conclusions: These results demonstrate that earlier and greater CSF penetration occurs as a result of the earlier and higher plasma peak with IV administration compared with PO or PR.

Intravenous acetaminophen for pain after major orthopedic surgery: an expanded analysis.

Abstract: Background and Methods: From the time that Sinatra et al. (Anesthesiology. 2005;102:822) was published to FDA apaproval of intravenous (IV) acetaminophen, an expanded analysis of the original raw study data became necessary for the regulatory submission. The following analyses were conducted: (1) sum of pain intensity differences over 24 hours (SPID24) using currently accepted imputation methods to account for both missing data and the effects of rescue; (2) efficacy results after the first 6 hours; (3) effects of gender, race/ethnicity, age, weight, surgical site, ASA Class, and serotonin antagonists; and (4) a stepwise regression analysis of why adverse events of nausea and vomiting were numerically (although not statistically) higher in the IV acetaminophen group compared with placebo. Results: Sum of pain intensity differences over 24 hours using a 0- to 100-mm visual analog scale was statistically significantly (P < 0.001) in favor of IV acetaminophen (n = 49) compared with placebo (n = 52). Time to rescue was found to be 3.9 and 2.1 hours, respectively, for total hip and knee arthroplasty compared with 0.8 hours for the placebo group. Rescue medication consumption, requests, and actual administration were all significantly lower in the IV acetaminophen group compared with placebo for each dosing interval, except in the 6- to 12-hours interval where a numerical trend was observed. Analysis of various subset variables demonstrated similar efficacy for each variable. A stepwise regression analysis demonstrated that AE reports of nausea and vomiting were most likely due to prerandomization events, particularly opioid consumption and presence of nausea prior to randomization. Conclusion: Repeated-dose 24-hours end points were found to be as robust as previously published results. IV acetaminophen efficacy and safety appeared to be unaffected by specific subset variables.▪

System and method for debugging computer program based on execution history

Abstract: A system and method are provided for enhanced navigation along execution time and code space in a debugger to assist a user in remediating errors, streamlining, or reverse engineering a computer program and the source code thereof. Snapshots of system states are recorded, a causality tree of commands is constructed through execution of the program to be debugged, and an intelligent display of system states captured during runtime and indexed or cross-referenced by time are displayed to the user in an intelligent manner to aid the user with certain debugging tasks. Additionally, further features in assisting the user to locate a root cause of an error or unexpected value and remediate that cause are also provided.

Self-aligned double patterning (SADP) compliant design flow

Abstract: Double patterning with 193nm optical lithography is inevitable for technology scaling before EUV is ready. In general, there are two major double patterning techniques (DPT): Litho-Etch-Litho-Etch (LELE) and sidewall spacer technology, a Self-Aligned Double Patterning technique (SADP). So far LELE is much more mature than SADP in terms of process development and design flow implementation. However, SADP has stronger scaling potential than LELE due to its smaller design rules on tip-tip and tip-side as well as its intrinsic self-align property. In this paper, we will explain in detail about how to enable a SADP-friendly design flow from multiple perspectives: design constructs, design rules, standard cell library and routing. In addition, the differences between SADP and LELE in terms of design, scaling capability and RC performance will be addressed.

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks

Abstract: Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.

Method and system for implementing parallel execution in a computing system and in a circuit simulator

Abstract: A method and mechanism for implementing a general purpose scripting language that supports parallel execution is described. In one approach, parallel execution is provided in a seamless and high-level approach rather than requiring or expecting a user to have low-level programming expertise with parallel processing languages/functions. Also described is a system and method for performing circuit simulation. The present approach provides methods and systems that create reusable and independent measurements for use with circuit simulators. Also disclosed are parallelizable measurements having looping constructs that can be run without interference between parallel iterations. Reusability is enhanced by having parameterized measurements. Revisions and history of the operating parameters of circuit designs subject to simulation are tracked.

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters

Abstract: Electronic beam lithography (EBL) is one of the promising emerging technologies in the sub-22 nm regime. In EBL, the desired circuit patterns are directly shot into the wafer, which overcomes the diffraction limit of light in the current optical lithography system. However, the low throughput becomes its key technical hurdle. In the conventional EBL system, each rectangle in the layout will be projected by one electronic shot through a variable shape beam (VSB). This could be extremely slow. As an improved EBL technology, character projection (CP) shoots complex shapes, so-called characters, in one time, by putting them into a predesigned stencil. However, only a limited number of characters can be employed, due to the area constraint. Those patterns, not contained by any character, are still required to be written by VSB. A key problem is how to select an optimal set of characters and pack them on the CP stencil to minimize total processing time. In this paper, we investigate a problem of electronic beam lithography stencil design with overlapped characters. Different from previous works, besides selecting appropriate characters, their placements on the stencil are also optimized in our framework. Specifically, we propose a Hamilton-path-based iterative algorithm to handle 1-D stencil design problem, and an effective simulated annealing framework for the generalized 2-D case with an efficient look-ahead sequence pair evaluation technique. The experimental results show that, compared to conventional stencil design methodology without overlapped characters, we are able to reduce total projection time by 51%.

FastRoute: an efficient and high-quality global router

Abstract: Modern large-scale circuit designs have created great demand for fast and high-quality global routing algorithms to resolve the routing congestion at the global level. Rip-up and reroute scheme has been employed by the majority of academic and industrial global routers today, which iteratively resolve the congestion by recreating the routing path based on current congestion. This method is proved to be the most practical routing framework. However, the traditional iterative maze routing technique converges very slowly and easily gets stuck at local optimal solutions. In this work, we propose a very efficient and high-quality global router--FastRoute. FastRoute integrates several novel techniques: fast congestion-driven via-aware Steiner tree construction, 3- bend routing, virtual capacity adjustment, multisource multi-sink maze routing, and spiral layer assignment. These techniques not only address the routing congestion measured at the edges of global routing grids but also minimize the total wirelength and via usage, which is critical for subsequent detailed routing, yield, and manufacturability. Experimental results show that FastRoute is highly effective and efficient to solve ISPD07 and ISPD08 global routing benchmark suites. The results outperform recently published academic global routers in both routability and runtime. In particular, for ISPD07 and ISPD08 global routing benchmarks, FastRoute generates 12 congestion-free solutions out of 16 benchmarks with a speed significantly faster than other routers.

Method and system for power delivery network analysis

Abstract: The subject application relates to a method and system for power delivery network analysis. The present disclosure is directed towards a computer-implemented method for displaying one or more results of a power delivery network (PDN) analysis associated with an electronic circuit design. The method may include extracting, using at least one processor, an electromagnetic (EM) model for each of one or more discontinuity structures associated with the electronic circuit design. The method may further include performing a power delivery network analysis of the electronic circuit design, the PDN analysis including a Method of Moments (MoM) calculation. The method may also include displaying a three dimensional image depicting one or more results of the PDN analysis. Numerous other features are also within the scope of the present disclosure.

Method and system for model-based design and layout of an integrated circuit

Abstract: A approach is described for allowing electronic design, verification, and optimization tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers.

GDRouter: interleaved global routing and detailed routing for ultimate routability

Abstract: Improving detailed routing routability is an important objective of a global router. In this paper, we propose GDRouter, an interleaved global routing and detailed routing algorithm for the ultimate routability i.e., detailed routing routability. The newly proposed router makes the global routing aware of detailed routing routability by correctly setting global capacity to reduce the inconsistency between the two stages. The final result contains both the detailed routing guided global routing and deailed routing solutions. Fast and efficient academic global routing and detailed routing tools FastRoute [1] and RegularRoute [2] are interleaved in GDRouter. In the Initial Capacity and Routing Weight Esitmation (ICRWE) phase, the weight for each global and detailed routing grid is calculated to make GDRouter aware of pin distribution based on a Gridded Voronoi Diagram method. Then the algorithm generates initial global capacity based on both local usage and global segment usage. In particular, Spine routing is utilized to estimate local usage. And a virtual routing i.e. fast implementations of FastRoute and RegularRoute, is performed to estimate global segment usage. The initial global capacity is applied in Full Routing phase to obtain detailed routing routability i.e., number of unassigned global segment. To further improve routability, in the following Iterative Test Routing (ITR) phase, GDRouter incrementally applies the interleaved global routing and detailed routing to adjust the global capcity based on detailed routing solution. To save runtime, GDRouter quits the loop if detailed routing routability stops improving or it reaches maximum iteration. Experimental results reveal that the newly proposed algorithm is capable of enhancing detailed routing routability. In particular, GDRouter reduces number of unassigned global segments by 90% for ISPD98 [3] derived testcases and around 60% for ISPD05/06 [4, 5] derived testcases with 2.9× runtime overhead.

Method and apparatus for AMS simulation of integrated circuit design

Abstract: A method to create an integrated circuit that includes digital and analog components comprising: displaying on a computer system display, user input to the computer system that specifies parameter information to determine a binding between an analog circuit design component and a digital circuit design component; saving the user specified parameter information within a file that also specifies at least a portion of the analog circuit design; associating the analog circuit design component a first design block of an integrated circuit that also includes a second digital design block coupled to the first design block; using parameter information to determine a binding between the first analog circuit design component and the first digital circuit design component; saving the determined binding in computer readable storage media.

Structural Characterization and Efficient Implementation Techniques for $A$ -Stable High-Order Integration Methods

Abstract: This paper presents structural characterization and performance enhancement strategies for the recently proposed A-stable and L-stable high-order integration methods based on the Obreshkov formula. It is demonstrated that although the Jacobian matrix in these methods has a bigger size than the Jacobian matrix in classical low-order methods, it enjoys a special structure that can be used to develop efficient factorization techniques. In addition, the paper proposes a method to reduce the number of Newton-Raphson iterations needed to converge in the large Jacobian domain.

Common path pessimism removal for hierarchical timing analysis

Abstract: A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock ports, creating launch and capture clocks, making exclusive clock groups of the launch clock and the capture clock for opposing clock ports to avoid the launch and capture clocks for each port affecting other internal data paths within the partition block, and associating common path pessimism removal information with a source latency of the capture clock to adjust timing at an end point of the internal data path.

Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy

Abstract: A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.

Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Recording and playback of trace and video log data for programs

Abstract: Recording and playback of trace log data and video log data for programs is described. In one aspect, a method for viewing log data recorded during execution of a program includes causing a display of recorded images depicting prior visual user interaction with the program during a particular time period. The method also includes causing a display of messages tracing and describing prior execution of the program during the particular time period. The display of the messages and the display of the recorded images are synchronized.

Virtual platforms: breaking new grounds

Abstract: The case for developing and using virtual platforms (VPs) has now been made. If developers of complex HW/SW systems are not using VPs for their current design, complexity of next generation designs demands for their adoption. In addition, the users of these complex systems are asking either for virtual or real platforms in order to develop and validate the software that runs on them, in context with the hardware that is used to deliver some of the functionality. Debugging the erroneous interactions of events and state in a modern platform when things go wrong is hard enough on a VP; on a real platform (such as an emulator or FPGA-based prototype) it can become impossible unless a new level of sophistication is offered. The priority now is to ensure that the capabilities of these platforms meet the requirements of every application domain for electronics and software-based product design. And to ensure that all the use cases are satisfied. A key requirement is to keep pace with Moore's Law and the ever increasing embedded SW complexity by providing novel simulation technologies in every product release. This paper summarizes a special session focused on the latest applications and latest use cases for VPs. It gives an overview of where this technology is going and the impact on complex system design and verification.

Timing budgeting of nested partitions for hierarchical integrated circuit designs

Abstract: In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a plurality of top level timing constraints and a description of the integrated circuit design defining a hierarchy of partitions having multiple levels with one or more nested partitions; generating timing models for each partition of the plurality of partitions in response to the description of the integrated circuit design; and concurrently generating timing budgets level by level for all partitions at each level, beginning with the lowest level to each next upper level of the hierarchy of the partitions in response to the description of the integrated circuit design, the timing models, and the plurality of top level timing constraints. Please see the detailed description and claims for other embodiments that are respectively disclosed and claimed.

Method and apparatus for identifying double patterning color-seeding violations

Abstract: A method for automatically performing a double patterning (DP) color-seeding check in order to discover color-seeding violations in an IC design layout. The method of some embodiments receives a layer of the IC design layout and performs an analysis on the layer of the design layout to determine several error paths. Each error path connects two color-seeding shapes that have a color-seeding violation. For each pair of shapes that has a color-seeding violation, the method of some embodiments displays a DP color-seeding violation marker on a graphical user interface (GUI) to visually assist a user to resolve the color-seeding violation.

Slew-aware buffer insertion for through-silicon-via-based 3D ICs

Abstract: Large parasitic capacitances of through-silicon-vias in 3D ICs cause signal slew and delay to increase. We propose a buffer insertion algorithm that further reduces delay by considering slew explicitly. Compared with the well-known van Ginneken algorithm and a commercial 2D tool, our algorithm improves full-chip timing with acceptable runtime overhead.

System and method for detecting and prescribing physical corrections for timing violations in pruned timing data for electronic circuit design defined by physical implementation data

Abstract: A system and method for expeditious operational timing signoff of a circuit design through a timing analysis and subsequent corrective or remedial optimization is performed with the goal of correlating timing between the physical implementation corrective optimizer module and the timing analysis module to reduce iterations therebetween. A physical optimizer in the correction module is imparted with knowledge of the physical implementation of the design to allow for legal, non-conflicting placement of corrective buffers or resizing of gates in accordance with the physical implementation data of the circuit design.

Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques

Abstract: Various embodiments identify some constraints for multiple mask designs of multi-patterning lithography processes for manufacturing an electronic design and colors multiple routing tracks in a layer of the electronic design with certain colors. These embodiments color fixed object(s) in the design with one or more of these certain colors based on coloring of the multiple routing tracks. Some embodiments further color movable object(s) based on results of coloring the fixed object(s) or coloring routing track(s). Some embodiments route the physical design with coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Multiple-patterning conflicts may be detected based on the coloring of fixed object(s), coloring of movable object(s), or routing connectivity. Some embodiments route with search-and-repair strategy(ies) to improve or resolve conflict(s). Some embodiments color objects upon their creation, and the layout is thus multiple-patterning design rule clean as constructed.

Method and apparatus for low-pin count testing of integrated circuits

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Method and apparatus for multi-die thermal analysis

Abstract: Some embodiments of the invention provide a method for performing thermal analysis of a multi-die integrated circuit (IC) design layout. The thermal analysis produces a temperature distribution for analyzing internal properties of each die within the multi-die design and for analyzing thermal interactions between two or more dies of the design based on an internal configuration of the two or more dies. Therefore, in some embodiments, the temperature distribution shows a temperature distribution for each die and the individual temperature distributions show varying temperature across each of the dies. Some embodiments reduce the number of iteration required to perform the thermal analysis by constructing a high quality preconditioner based on thermal conducting segments introduced to model thermal effects at the boundaries between two dies.

Power domain crossing interface analysis

Abstract: A method is provided to test an integrated circuit design for power management circuit design errors comprising: configuring a computer to identify multiple power domain crossing paths between pairs of power domains; identify one or more power related constraints associated with such power domain crossing paths; and group power domain crossing paths between matching power domain pairs that are associated with matching power related constraints.

Custom on-chip sensors for post-silicon failing path isolation in the presence of process variations

Abstract: This work offers a framework for predicting the delays of individual design paths at the post-silicon stage which is applicable to post-silicon validation and delay characterization. The prediction challenge is mainly due to limited access for direct delay measurement on the design paths after fabrication, combined with the high degree of variability in the process and environmental factors. Our framework is based on using on-chip delay sensors to improve timing prediction. Given a placed netlist at the pre-silicon stage, an optimization procedure is described which automatically generates the sensors subject to an area budget and available whitespace on the layout, in the presence of process variations. Each sensor is then generated as a sequence of logic gates with an approximate location on the layout at the pre-silicon stage. The on-chip sensor delay is then measured to predict the delays of individual design paths with less pessimism. In our experiments, we show that custom on-chip sensors can significantly increase the rate of predicting if a specified set of paths are failing their timing requirements.

Diagnosis of Board-Level Functional Failures Under Uncertainty Using Dempster–Shafer Theory

Abstract: Despite recent advances in structural test methods, the diagnosis of the root cause of board-level failures for functional tests remains a major challenge. A promising approach to address this problem is to carry out fault diagnosis in two phases-suspect faulty components on the board or modules within components (together referred to as blocks in this paper) are first identified and ranked, and then fine-grained diagnosis is used to target the suspect blocks in a ranked order. We propose a new method based on dataflow analysis and Dempster-Shafer (DS) theory for ranking faulty blocks in the first phase of diagnosis. The proposed approach transforms the information derived from one functional test failure into multiple-stage failures by partitioning the given functional test into multiple stages. A measure of “belief” is then assigned to each block based on the knowledge of each failing stage, and the DS theory is subsequently used to aggregate the beliefs from multiple failing stages. Blocks with higher beliefs are ranked on the top of the candidate list. Simulations on an industry design for a network interface application as well as on an open source system-on-a-chip show that the proposed method can provide accurate ranking for most board-level functional failures.

Optimal slack-driven block shaping algorithm in fixed-outline floorplanning

Abstract: This paper presents an efficient, scalable and optimal slack-driven shaping algorithm for soft blocks in non-slicing floorplan. The proposed algorithm is called SDS. Different from all previous approaches, SDS is specifically formulated for fixed-outline floorplanning. Given a fixed upper bound on the layout width, SDS minimizes the layout height by only shaping the soft blocks in the design. Iteratively, SDS shapes some soft blocks to minimize the layout height, with the guarantee that the layout width would not exceed the given upper bound. Rather than using some simple heuristic as in previous work, the amount of change on each block is determined by systematically distributing the global total amount of available slack to individual block. During the whole shaping process, the layout height is monotonically reducing, and eventually converges to an optimal solution. We also propose two optimality conditions to check the optimality of a shaping solution. To validate the efficiency and effectiveness of SDS, comprehensive experiments are conducted on MCNC and HB benchmarks. Compared with previous work, SDS is able to achieve the best experimental result with significantly faster runtime.

Method and system for implementing top down design and verification of an electronic design

Abstract: Disclosed is a method and system for performing design and verification using stepwise refinement techniques, which can also include or be referred to as “top-down” design verification. With the present stepwise refinement approach, the electronic design can be acted upon at different levels of abstraction, but with approximately the same level of resolution at each abstraction level. A strong relationship of consistency exists between the successive abstraction levels of the design. On account of this consistency, properties that are established or true at one level of the design remain true for all subsequent levels of abstraction of the design. The present approach also allows designers to more efficiently and accurately perform hardware/software co-design. For the co-design process, consistency between different levels of abstraction allows a designer to safely implement a systematic and concurrent divide-and-conquer approach to the hardware and/or software elements in a design.