Showing papers in "Analog Integrated Circuits and Signal Processing in 2007"
TL;DR: In this paper, a compact active inductor circuit is proposed based on the gyrator-C approach with both transconductance stages realized by MOS transistors in common-source configuration.
Abstract: A compact active inductor circuit is proposed. The circuit is based on the gyrator-C approach with both transconductance stages realized by MOS transistors in common-source configuration. The circuit has minimal number of transistors, is suitable for low voltage operation, offers a wide inductive band, high quality factor and low power dissipation. Simulation results are provided for a 0.13 μm CMOS process with 1.2 V supply voltage.
67 citations
TL;DR: In this article, a transadmittance-mode (TM) universal filter with three inputs and a single output is presented, which employs only two current differencing transconductance amplifiers (CDTAs), two capacitors one of which is permanently grounded and as many resistors.
Abstract: A new transadmittance-mode (TM) universal filter with three inputs and a single output is presented. The circuit employs only two current differencing transconductance amplifiers (CDTAs), two capacitors one of which is permanently grounded and as many resistors. The proposed circuit realizes lowpass (LP), highpass (HP), bandpass (BP), notch and allpass (AP) functions from the same configuration. Both the active and passive sensitivities are no more than unity. The natural frequency ?o and bandwidth ?o/Q are independently and electronically tunable. PSPICE simulation results are included.
67 citations
TL;DR: In this article, the effect of fringing field is modeled as a variable serial capacitor and a robust control scheme is constructed using the theory of input-to-state stabilization (ISS) and backstepping state feedback design.
Abstract: Though the effect of fringing field in electrostatic parallel-plate actuators is a well-understood phenomenon, the existing formulations often result in complicated mathematical models from which it is difficult to determine the deflection of the moving plate for given voltages and hence, they are not suitable for accurate actuation control. This work presents a new formulation for tackling the fringing field, in which the effect of fringing field is modeled as a variable serial capacitor. Based on this model, a robust control scheme is constructed using the theory of input-to-state stabilization (ISS) and backstepping state feedback design. This method allows loosening the stringent requirements on modeling accuracy without compromising the performance. The stability and the performance of the system using this control scheme are demonstrated through both stability analysis and numerical simulation.
66 citations
TL;DR: In this article, a voltage-mode universal biquad with single input and multiple outputs has been reported to simultaneously achieve all of the advantageous features: (i) employment of only two differential difference current conveyor (DDCC), (ii) employed two grounded capacitors, (iii) employed only three resistors, and (iv) simultaneously realize voltage mode low pass, band-pass, high pass, notch and all pass filter signals from the five output terminals, respectively, orthogonal control of? o and Q, low input impedance and can be cascadable
Abstract: Despite the extensive literature on current conveyor-based voltage-mode universal biquads with single input and multiple outputs, no filter circuit has been reported to simultaneously achieve all of the advantageous features: (i) employment of only two differential difference current conveyor (DDCC), (ii) employment only two grounded capacitors, (iii) employment only three resistors, (iv) simultaneously realize voltage-mode low-pass, band-pass, high-pass, notch and all-pass filter signals from the five output terminals, respectively, (v) orthogonal control of ? o and Q, (vi) low input impedance and can be cascadable (vii) no need to employ inverting type input signals, and (viii) no need to impose component choice except realizing the all-pass filter signal.
59 citations
TL;DR: In this article, an analytical frequency-dependent resistance model for integrated spiral inductors is proposed, which provides a fast alternative to field solver-based approaches with typical errors of less than 2.6 percent while surpassing the accuracy of several other analytical modeling techniques by an order of magnitude.
Abstract: For integrated spiral inductor synthesis, designers and design automation tools require efficient modeling techniques during the initial design space exploration process. In this paper, we introduce an analytical frequency-dependent resistance model for integrated spiral inductors. Based on our resistance formulation, we have developed a systematic technique for creating wide-band circuit models for accurate time domain simulation. The analytical resistance model provides a fast alternative to field solver-based approaches with typical errors of less than 2.6 percent while surpassing the accuracy of several other analytical modeling techniques by an order of magnitude. Furthermore, the wide-band circuit generation technique captures the frequency-dependent resistance of the inductor with typical errors of less than 3.2 percent.
56 citations
TL;DR: In this article, a transistor-only active inductor with an all-NMOS signal path is presented, where the varactor-augmented parasitic capacitance at the only internal node can be partially or fully compensated to permit realizing unlimited values of Q, with little frequency and no power-consumption penalties.
Abstract: A transistor-only CMOS active-inductor with an all-NMOS signal path is presented. By tuning the varactor-augmented parasitic capacitance at the only internal node the circuit losses from submicron MOSFETs can be partially or fully compensated to permit realizing unlimited values of Q, with little frequency and no power-consumption penalties. Transistor-only second-order bandpass filters using the active inductor were built in the TSMC 0.18-μm CMOS process, and high filter Q was obtained by tuning the varactor. The highest center frequency measured was f 0 = 5.7 GHz for 0.2-μm gate lengths and the maximum repeatably measured Q was 665. Lower Qs can be obtained by reducing the capacitive compensation or by adjusting the circuit biasing. f 0 and Q are tunable via separate varactors. IIP 3 and input 1-dB compression point were simulated as 0.523 VPP and 0.128 VPP (?1.65 and ?13.9 dBm from a 50-? source) at 5.7 GHz with Q = 100 and midband gain equal 4.7 dB. For the same conditions, the output noise and noise figure (R S = 50 k?) were simulated to be 0.8 μV/Hz1/2 and 25.6 dB, respectively. The filter core occupies an area of 26.6 μm × 30 μm and dissipates 4.4 mW at 5.4 GHz from a 1.8-V power supply. As the circuits use only MOSFETs they are fully compatible with standard digital CMOS processes. f 0 statistics were obtained by measuring 40 chips at identical biasing condition.
50 citations
TL;DR: The proposed heuristic is applied to design SI class AB grounded gate memory cells and they are well known to be improved cells, and the optimization procedure, developed with help of C++ software, allows automatic design of the cell.
Abstract: Optimally designing switched current (SI) memory cells is a hard task. In addition, it is usually limited to the design of ideal cells. Thus, in this paper we deal with optimizing these cells and precisely real ones using a heuristic. Since SI class AB grounded gate memory cells are well known to be improved cells, we applied the proposed heuristic to design this kind of cells. Also, besides maximizing performances and minimizing famous error sources, we focus on optimally sizing transistors forming switches and bias sources. The optimization procedure, developed with help of C++ software, allows automatic design of the cell. It is also highlighted in the followings.
34 citations
TL;DR: In this paper, the authors developed a dynamic multi-point rational interpolation method based on Krylov subspace techniques to generate reduced order models for passive components and interconnects that are accurate across a wide-range of frequencies.
Abstract: The efficient modeling of integrated passive components and interconnects is vital for the realization of high performance mixed-signal systems. In this paper, we develop a dynamic multi-point rational interpolation method based on Krylov subspace techniques to generate reduced order models for passive components and interconnects that are accurate across a wide-range of frequencies. We dynamically select interpolation points by applying a cubic spline-based algorithm to detect complex regions in the system's frequency response. The results indicate that our method provides greater accuracy than techniques that apply uniform interpolation points.
34 citations
TL;DR: In this article, the authors presented a modeling methodology for fully integrated inductively degenerated cascode ultrawideband low noise amplifiers (LNA) with generalized filter-based impedance matching networks.
Abstract: In this paper, we present a modeling methodology for fully integrated inductively degenerated cascode ultrawideband low noise amplifiers (LNA) with generalized filter-based impedance matching networks. Our accurate analytical models capture the impact of device and passive component parasitics and transistor short channel effects to generate accurate designs. Utilizing our methodology, we are able to accurately generate an ultrawideband LNA in the 3.1---10.6 GHz frequency band using third and fifth order Chebyshev filters as input impedance matching networks. The speed and accuracy of the proposed analytical model will facilitate rapid design space exploration for ultrawideband LNAs.
31 citations
TL;DR: The proposed FDCII and its applications are simulated using CMOS 0.35 μm technology and the application of the FDCCII to realize variable gain amplifier, fully differential integrator, and fully differential second order bandpass filter are given.
Abstract: This paper presents a new CMOS fully differential second-generation current conveyor (FDCCII). The proposed FDCCII is based on a fully differential difference transconductor as an input stage and two class AB output stages. Besides the proposed FDCCII circuit is operating at supply voltages of ±1.5 V, it has a total standby current of 380 ?A. The application of the FDCCII to realize variable gain amplifier, fully differential integrator, and fully differential second order bandpass filter are given. The proposed FDCII and its applications are simulated using CMOS 0.35 ?m technology.
29 citations
TL;DR: In this paper, a design optimization methodology for switchable multi-port spiral inductors in fully integrated wireless systems was developed to simultaneously maximize the inductor's performance for multiple inductance values and operating frequencies.
Abstract: In this paper, we develop a design optimization methodology for switchable multi-port spiral inductors in fully integrated wireless systems. The methodology simultaneously maximizes the inductor's performance for multiple inductance values and operating frequencies. We utilize multi-level optimization techniques to efficiently design the geometry of the switchable inductor structure. The methodology can produce designs with significantly larger quality factors than those obtained by optimizing the inductor design for a single inductance value and operating frequency.
TL;DR: An impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications that has been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SoP) technology for low power, low cost and small size integration.
Abstract: In this paper, we describe an impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications. Different architectures have been studied for base station and sensor nodes. The base station node uses coherent UWB architecture because of the high performance and good sensitivity requirements. However, to meet complexity, power and cost constraints, the sensor module uses a novel non-coherent architecture that can autonomously detect the UWB signals. The radio modules include a transceiver block, a baseband processing unit and a power management block. The transceiver block includes a Gaussian pulse generator, a multiplier, an integrator and timing circuits. For long range applications, a wideband low noise amplifier (LNA) is included in the transceiver of the sensor module, whereas in short range applications it is simply eliminated to further reduce the power consumption. In order to verify the proposed system concept, circuit level implementation is studied using 1.5 V 0.18 ?m CMOS technology. Finally, the UWB radio modules have been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SoP) technology for low power, low cost and small size integration. A small low cost, double-slotted, Knight's helm antenna is embedded in the LCP substrate, which shows stable characterization and a return loss better than ?10 dB over the UWB band.
TL;DR: In this paper, the linearity of frequency modulation in voltage controlled inverter ring oscillators for non feedback sigma delta converter applications is studied through theoretical models of the oscillator operating at supply voltages above and below the threshold voltage of a transistor, bringing the transistors in respectively strong and weak inversion.
Abstract: In this paper linearity of frequency modulation in voltage controlled inverter ring oscillators for non feedback sigma delta converter applications is studied. The linearity is studied through theoretical models of the oscillator operating at supply voltages above and below the threshold voltage of a transistor, bringing the transistors in respectively strong and weak inversion. The theoretical results are tested with more advanced models through spectreRF simulations. A soft rail approach implemented to improve linearity in weak inversion is proposed and demonstrated. The influence from voltage noise, process variations and temperature variations have also been simulated to indicate the advantages of having the soft rail bias transistor in the VCO.
TL;DR: In this article, a comparative study of integrated submicron CMOS quadrature voltage-controlled oscillator designs based on LC resonator tanks operating at gigahertz frequencies is presented.
Abstract: This review paper presents a comparative study of published integrated submicron CMOS quadrature voltage-controlled oscillator designs, based on LC resonator tanks operating at gigahertz frequencies. Although special reference to phase noise reduction is made, the comparison also concerns issues such as power consumption, tuning range and the phase accuracy of the quadrature signals. The effect of supply voltage reduction on the choice of the oscillator topology is also included in the discussion.
TL;DR: In this article, two new CMOS realizations for the inverting current conveyor (ICCII) were presented, which offer enhanced features compared to previously reported ICCII, and new oscillator circuits based on using the ICCII as an active element are presented.
Abstract: This paper presents two new CMOS realizations for the inverting current conveyor (ICCII). The proposed realizations offer enhanced features compared to previously reported ICCII. Also new oscillator circuits based on using the ICCII as an active element are presented. The presented oscillator circuits have the advantage that both the oscillation frequency and the oscillation condition can be adjusted independently. Also another application to the ICCII, which is a floating inductor, is proposed. A second order low pass filter using the proposed floating inductor is simulated and compared with the ideal result. The proposed ICCIIs and the presented applications are tested with SPICE simulations using CMOS 0.35 μm technology to verify the theoretical results.
TL;DR: In this article, a novel ideal op-amp based counterexample to this suggestion is presented, which serves to substantiate the findings in a recent Letter and a discussion relating to the finite gain of Op-amp is included.
Abstract: It has been suggested in many textbooks that, given a closed-loop system, oscillation will commence and build up therein if the magnitude of loop gain is greater than unity at the frequency at which the angle of loop gain is zero degree. A novel ideal op-amp based counterexample to this suggestion is presented. The Letter serves to substantiate the findings in a recent Letter. A discussion relating to the finite gain of op-amp is included.
TL;DR: In this paper, a new versatile class AB low-voltage second generation current conveyor based on CMOS inverters operating in transconductance mode is presented, which is able to operate at low supply voltages and offers numerous advantages like class AB operation, large voltage and current swing.
Abstract: A new versatile class AB low-voltage second generation current conveyor based on CMOS inverters operating in transconductance mode is presented in this letter. Against traditional design based on CCII+, the circuit is able to operate at low supply voltages and offers numerous advantages like class AB operation, large voltage and current swing, synthesis from digital inverters. Simulation results from a typical 0.35 μm CMOS process had demonstrated the circuit capability to operate at high frequency over wide voltage and wide current swings. The proposed circuit operation has been acted from measurements with the HEF4069UBP from Philips semiconductors [1].
TL;DR: This work presents the design and implementation of a 2.4 GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25 μm CMOS with trade-off made over the design boundaries of the different building blocks to optimize the overall system performance.
Abstract: This work presents the design and implementation of a 2.4 GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25 μm CMOS. The prototype integrates a low-IF receiver analog front-end (low noise amplifier, double-balanced down-converter, band-pass-filtered AGC loop, and ASK demodulator) and a direct-conversion transmitter analog front-end (20 MHz IF PLL with well-defined amplitude control circuit, ASK modulator, up-converter, and output buffer) on a single chip together with one integrated RF oscillator and two LO buffers. Trade-off has been made over the design boundaries of the different building blocks to optimize the overall system performance. All building blocks feature the circuit topologies that enable comfortable operation at low power consumption. As a result, the IC works at a 2.5 V power supply, while only consuming 15 mW in receiver (RX) mode and 14 mW in transmitter (TX) mode. To build a complete transceiver for the endoscopy capsule system, only an antenna, a duplexer, and a digital controller are needed besides the presented analog front-end chip.
TL;DR: Singh, V. as discussed by the authors reviewed the reported circuit examples and presented the treatment of Barkhausen oscillation criterion and showed that the failure of this criterion can be justified by counterexamples.
Abstract: The comment is related to the recently published papers given in [Singh, V. (2006). Analog Integrated Circuits and Signal Processing, 48, 251---255; Singh, V. (2007). Analog Integrated Circuits and Signal Processing, 50, 127---132.] which depict the failure of Barkhausen oscillation building up criterion. Many counterexamples have been given in order to substantiate such viewpoint. We would like to review these reported circuit examples and present the treatment of Barkhausen oscillation criterion.
TL;DR: A low noise 0.9 GHz FBAR clock consisting of an oscillator and divider circuit for single-sided-to-differential conversion for a high-speed interleaved pipeline A/D-converter showed very good jitter and phase noise performance.
Abstract: A low noise 0.9 GHz FBAR clock consisting of an oscillator and divider circuit for single-sided-to-differential conversion for a high-speed interleaved pipeline A/D-converter was designed, realized with an in-house FBAR and a commercial 0.35 ?m CMOS process, and tested. The circuit showed very good jitter and phase noise performance. A temperature coefficient of ---47 ppm/K was measured.
TL;DR: In this article, a peak cancellation technique is proposed to reduce the peak-to-average power ratio (PAPR) of the input signal, which is based on using peak cancellation to reduce peak re-growth.
Abstract: This paper describes a new efficient crest factor reduction technique for wideband applications. The technique is based on using peak cancellation to reduce the peak-to-average power ratio (PAPR) of the input signal. Conventional iterative peak cancellation requires several iterations so as to converge into the targeted PAPR, since filtering causes peak re-growth. The proposed algorithm is able to eliminate several iterations, which subsequently saves hardware resources. In numerical simulations using four WCDMA carriers, it achieves a PAPR of 5.7 dB with a fixed EVM of 10%. A 240 W PEP Class AB power amplifier was utilized to verify the performance of the proposed technique and demonstrate the efficiency gains. The measured results demonstrate that this algorithm can enhance the efficiency of our PA by up to 6.6%, when compared to the efficiency without the PAPR technique.
TL;DR: In this paper, a topological form for the synthesis of filters with high dynamic range is proposed and a biquad notch/all-pass filter is shown in conformity with the given topology form.
Abstract: The signal handling capability of the filters is called dynamic range. In this paper, a topological form for the synthesis of filters with high dynamic range is proposed. A biquad notch/all-pass filter is shown in conformity with the given topological form. It is shown that there is a trade-off between dynamic range and high input impedance property. The presented circuit is compared with other notch filters in the literature. It has less number of components, better high-frequency response and dynamic range compared to others. Since the circuit includes a minimum number of resistors, it can easily provide electronically tunable circuits through resistor/controlled current conveyor replacement. Simulations are performed to verify the theoretical results. Routh-Hurwitz stability analyses are also given.
TL;DR: In this paper, a new idea for generation of quadrature signals on chip is presented based on a passive RC polyphase filter, where the resistive parts are made active by using inverters.
Abstract: A new idea for generation of quadrature signals on chip is presented The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters The active filter combines quadrature generation, isolation, and gain without losing quadrature performance compared to a regular RC polyphase filter The filter technique is demonstrated in a 10 GHz front-end application where a broadband VCO, having a tuning range of 144 GHz, drives an active polyphase filter to generate quadrature LO signals According to simulations the quadrature phase error shows a typical tuned behavior and stays below 08° for the complete tuning range Since the signal amplitude is high throughout the filter the noise is low, below 160 dBc/Hz at 10 MHz offset The high amplitude also reduces the need for high gain tuned buffers, thereby enabling significant reductions in chip area
TL;DR: In this paper, a new circuit configuration for the realization of a single-resistance-controlled Sinusoidal oscillator is presented which uses only one positive four terminal floating nullor (PFTFN) along with two grounded capacitors and five resistors.
Abstract: A new circuit configuration for the realization of a single-resistance-controlled Sinusoidal oscillator is presented which uses only one positive four terminal floating nullor (PFTFN) along with two grounded capacitors and five resistors and offers independent control of the frequency of oscillation as well as the condition of oscillation through separate resistors. Experimental results showing the workability of the proposed circuit have been given.
TL;DR: A high order curvature compensation technique for current reference generator which exploits the I–V characteristic of MOS to achieve ISC (Tm) (m ≥ 2) is described.
Abstract: A high order curvature compensation technique for current reference generator which exploits the I---V characteristic of MOS to achieve I SC (T m ) (m ? 2) is described. I SC (T m ) is a self-compensated current which corrects its negative three-order TC (Temperature Coefficient) and linear TC by itself. Then, I (T 2) is achieved also by exploiting the I---V characteristic of MOS, for correcting the other negative high order parts of I SC (T m ). This circuit operates on a 1.8 V power supply and is compatible with a standard n-well 0.5-μm digital CMOS process. The circuit realizes a temperature coefficient of 0.7 ppm/°C, a deviation of the simulated output current of 0.011% from ?20°C to + 150°C and 97.5 dB PSRR through HSPICE simulation.
TL;DR: In this paper, an adaptable receiver architecture and a reconfigurable component design technique using a switchable passive network are proposed to verify the proposed design technique, the reconfigured mixer and QVCO are designed using a flexible matching network and flexible LC tank, respectively.
Abstract: For successful implementation of a multi-standard receiver, a reconfigurable receiver architecture and a reconfigurable component design technique are essential In this paper, an adaptable receiver architecture and a reconfigurable RF design technique using a switchable passive network are proposed To verify the proposed design technique, the reconfigurable mixer and QVCO are designed using a flexible matching network and flexible LC tank, respectively The measurement results of each component well prove the usefulness of the switchable passive network
TL;DR: Piskorowski et al. as discussed by the authors presented a theoretical concept of time-varying Butterworth filters with compensated group delay response, which can provide both a constant delay and a maximally flat magnitude response over the desired frequency band, while ensuring the transient of the designed filter as short as possible.
Abstract: In this paper, we will address the question of how to design a continuous-time filter that provides both a constant delay and a maximally flat magnitude response over the desired frequency band, and at the same time ensures the transient of the designed filter as short as possible. The paper presents a theoretical concept of time-varying Butterworth filters with compensated group delay response. Using the compensated Butterworth filter, we introduce time-varying parameters to its structure for the purpose of the minimization of the transient that was lengthened because of the process of the compensation. Results verifying the effectiveness of the proposed approach are presented and compared to the traditional filters. This paper is an updated and extended version of Piskorowski, J. (2006). Analog Integrated Circuits and Signal Processing, 47, (2):233---241.
TL;DR: In this article, a modified model of solid state power amplifiers is presented and a predistorter structure is suggested to compensate both AM/AM and AM/PM conversion characteristics of a power amplifier.
Abstract: In this paper we present a modified model of solid state power amplifiers. Also using the mathematical concept of best approximation in Hilbert spaces, a predistorter structure is suggested to compensate both AM/AM and AM/PM conversion characteristics of a solid state power amplifier. To verify the effects of this linearization we generally consider it in a QAM signal transmission in an additive white Gaussian noise channel and the results are compared with the ideal linear case. It is shown that the presented method is able to compensate the nonlinearity up to a good extent. The performance of proposed method has been analyzed in frequency domain through spectrum simulations. To prove the validity of presented method we have made similar considerations on continuous spectrum.
TL;DR: In this paper, the authors present an efficient method of determining the optimized layout of on chip spiral inductor by developing layout design parameter bound curves for a large range of physical inductance values that satisfy the same area specification.
Abstract: In this paper we present an efficient method of determining the optimized layout of on chip spiral inductor. The method initially identifies the feasible region of optimization by developing layout design parameter bound curves for a large range of physical inductance values that satisfies the same area specification. For any desired inductance value the upper and lower bounds of the optimization variables are determined graphically. An enumeration algorithm implemented finds the global optimum layout that gives the highest quality factor in less than 1 s of CPU time with less function evaluations. The optimization method also gives the performance of all possible combinations that results the same inductance value. Subsequently important fundamental tradeoff of the design like quality factor and area, quality factor and inductance, quality factor and operating frequency, maximum quality factor and the peak frequency is explored in few seconds. The method also gives other valuable information such as sensitivity of the inductance and quality factor to the layout design parameters. The accuracy of the proposed method is verified using a 3D electromagnetic simulator.
TL;DR: In this article, a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications is described, which is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB's.
Abstract: This paper describes a 10-bit 200-MHz CMOS current steering digital-to-analog converter (DAC) for HDTV applications. The proposed 10-bit DAC is composed of a unit decoded matrix for 6 MSBs and a binary weighted array for 4 LSB's, considering linearity, power consumption, routing area, and glitch energy. A new switching scheme for the unit decoded matrix is developed to improve linearity further. Cascade current sources and differential switches with deglitch latch improve dynamic performance. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3 LSB and 0.2 LSB, respectively. The converter achieves a spurious-free dynamic range (SFDR) of above 55 dB over a100-MHz bandwidth and low glitch energy of 1.5 pVs. The circuit is fabricated in a 0.25 μm CMOS process and occupies 0.91 mm2. When operating at 200 M Sample/s, it dissipates 82 mW from a 3.3 V power supply.