Showing papers in "International Journal of Circuit Theory and Applications in 2011"
TL;DR: Three models of a constant-phase element consisting of passive R and C components are described, which can be used for practical realization of fractional analog differentiators and integrators, fractional oscillators, chaotic networks or for analog simulation of fractionsal control systems.
Abstract: SUMMARY
The paper describes models of a constant-phase element consisting of passive R and C components. The models offer any input impedance argument (phase) between −90° and 0° over a selectable frequency band covering several decades. The design procedure makes it possible to choose values of average phase, phase ripple, frequency bandwidth, and total number of R and C elements. The model can cover three frequency decades with as few as five resistors and five capacitors. The models can be used for practical realization of fractional analog differentiators and integrators, fractional oscillators, chaotic networks or for analog simulation of fractional control systems. Copyright © 2011 John Wiley & Sons, Ltd.
175 citations
TL;DR: The current paper presents a novel Schmitt trigger using two second-generation current conveyors and four resistors and its application as a relaxation oscillator that reports low sensitivities and has features suitable for VLSI implementation.
Abstract: The current paper presents a novel Schmitt trigger using two second-generation current conveyors and four resistors and its application as a relaxation oscillator. The performance of the proposed circuit is examined using Cadence and the model parameters of a 0.6µm CMOS process. The obtained results demonstrate excellent agreement with the theoretical values. The measured results based on commercially available current feedback operational amplifiers (AD 844 AN) are included and the non-idealities are also examined. The topology reports low sensitivities and has features suitable for VLSI implementation. Copyright © 2010 John Wiley & Sons, Ltd.
(The current paper presents a novel Schmitt trigger using two second-generation current conveyors and four resistors and its application as a relaxation oscillator. The performance of the proposed circuit is examined using Cadence and the model parameters of a 0.6 m CMOS process. The obtained results demonstrate excellent agreement with the theoretical values.)
71 citations
TL;DR: A method is proposed for solving the two key problems facing quantum neural networks: introduction of nonlinearity in the neuron operation and efficient use of quantum superposition in the learning algorithm.
Abstract: A method is proposed for solving the two key problems facing quantum neural networks: introduction of nonlinearity in the neuron operation and efficient use of quantum superposition in the learning algorithm. The former is indirectly solved by using suitable Boolean functions. The latter is based on the use of a suitable nonlinear quantum circuit. The resulting learning procedure does not apply any optimization method. The optimal neural network is obtained by applying an exhaustive search among all the possible solutions. The exhaustive search is carried out by the proposed quantum circuit composed of both linear and nonlinear components. Copyright © 2009 John Wiley & Sons, Ltd.
68 citations
TL;DR: A novel current-mode solution suitable for the square waveform generation is proposed, which utilizes only two positive second-generation current conveyors as active blocks, six resistors and a capacitor, based on a current differentiation instead of voltage integration, so avoiding circuit limitations due to the node saturation effects.
Abstract: SUMMARY
In this paper, we propose a novel current-mode solution suitable for the square waveform generation. The designed oscillator, which utilizes only two positive second-generation current conveyors as active blocks, six resistors and a capacitor, is based on a current differentiation, instead of voltage integration, typical of developed solutions both in voltage-mode and in current-mode approaches, so avoiding circuit limitations due to the node saturation effects. The proposed circuit has been designed, as an integrated solution at transistor level, in a standard CMOS technology, with low-voltage (± 1V) and low-power (430µW) characteristics. Simulation results have confirmed the good circuit behaviour, also for working temperature drifts, showing good linearity in a wide oscillation frequency range, which can be independently adjusted through either capacitive (in the range pF − µF) or resistive (in the range M Ω–G Ω) external passive components. Waiting for the chip fabrication, preliminary measurements have been performed using a laboratory breadboard employing the CCII with AD844 commercial component and sample capacitors and resistors. The experimental results have shown good agreement with both simulations and theoretical expectations. Copyright © 2011 John Wiley & Sons, Ltd.
62 citations
TL;DR: Performance results using the proposed discrete-time formulations are found to converge to the analytical results of FOD and FOI, in the continuous-time domain.
Abstract: In this paper, new discretized models for fractional-order differentiator (FOD) (sr) and integrator (FOI) (s−r) using first-order and higher order operators are proposed. The expansions for FOIs of the first-order s-to-z transform proposed by Hsue et al. are obtained by using the Taylor series and continued fraction expansion techniques. Second-order Schneider operator and third-order Al-Alaoui–Schneider–Kaneshige–Groutage (Al-Alaoui–SKG) rule have also been fractionalized to obtain expansions of FODs by using the Taylor series. Specifically, in this paper, Hsue operator based on third-order and fourth-order models of FOI, Schneider operator as well as Al-Alaoui–SKG rule based on third-order, fourth-order, fifth-order and sixth-order models of FOD have been suggested. The stability of the proposed models has been investigated and the unstable ones were stabilized by the pole reflection method. The performance of the proposed models has been compared with that of recent FOD and FOI models based on the Al-Alaoui operator. Performance results using the proposed discrete-time formulations are found to converge to the analytical results of FOD and FOI, in the continuous-time domain. Copyright © 2010 John Wiley & Sons, Ltd.
60 citations
TL;DR: A low-voltage input stage constructed from bulk-driven PMOS transistors is proposed, based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk- driven structures.
Abstract: A low-voltage input stage constructed from bulk-driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk-driven structures. The proposed input stage offers also extended input common-mode range under low supply voltage in relevant to a gate-driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common-mode voltage stabilization and a latch-up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.
59 citations
TL;DR: Digital architectures for the circuit realization of multivariate piecewise‐linear (PWL) functions are reviewed and compared and two architectures with different levels of parallelism/complexity are proposed.
Abstract: Digital architectures for the circuit realization of multivariate piecewise-linear (PWL) functions are reviewed and compared. The output of the circuits is a digital word representing the value of the PWL function at the n-dimensional input. In particular, we propose two architectures with different levels of parallelism/complexity. PWL functions with n = 3 inputs are implemented on an FPGA and experimental results are shown. The accuracy in the representation of PWL functions is tested through three benchmark examples, two concerning three-variate static functions and one concerning a dynamical control system defined by a bi-variate PWL function. Copyright © 2009 John Wiley & Sons, Ltd.
58 citations
TL;DR: An exact solution discrete-time model able to predict both instability phenomena is derived and it can be used to obtain the useful operation region in the multi-dimensional design parameter space from time domain simulations in a very fast and accurate manner.
Abstract: In this paper, the dynamical behavior of a full bridge DC–AC buck inverter controlled by fixed frequency and PWM is studied. After showing that the system can undergo both period-doubling and Neimark–Sacker bifurcation at the fast scale (switching period) by using the exact switching model, an exact solution discrete-time model able to predict both instability phenomena is derived. The model is obtained without making the quasi-static approximation and it can be used to obtain the useful operation region in the multi-dimensional design parameter space from time domain simulations in a very fast and accurate manner. Based on the study of the system, some design guidelines are provided. Copyright © 2010 John Wiley & Sons, Ltd.
45 citations
TL;DR: A new four-dimensional continuous-time autonomous hyperchaotic Lorenz-type system is introduced and analyzed and explicit formulae for estimating the ultimate bound and positive invariant set of the system are derived by constructing a family of generalized Lyapunov functions.
Abstract: A new four-dimensional continuous-time autonomous hyperchaotic Lorenz-type system is introduced and analyzed. This hyperchaotic system is not only visualized by computer simulation but also verified with bifurcation analysis and realized with an electronic circuit. Moreover, explicit formulae for estimating the ultimate bound and positive invariant set of the system are derived by constructing a family of generalized Lyapunov functions. The findings and results of this paper have good potential in control and synchronization of hyperchaos and their engineering applications. Copyright © 2010 John Wiley & Sons, Ltd.
45 citations
TL;DR: It is shown that the main model, which combines memristors' fluxes and charges, is index two, and this result is based on the use of a projector along the image of the leading matrix, in contrast to previous index analyses.
Abstract: In this paper we present several semistate or differential-algebraic models arising in nodal analysis of nonlinear circuits including memristors. The goal is to characterize the tractability index of these models under strict passivity assumptions, a key issue for the numerical simulation of circuit dynamics. We show that the main model, which combines memristors' fluxes and charges, is index two. From a technical point of view, this result is based on the use of a projector along the image of the leading matrix, in contrast to previous index analyses. For charge-controlled memristors, the elimination of fluxes yields an index one system in topologically nondegenerate circuits, and an index two model otherwise. Analogous results are also proved to hold for flux-controlled memristors. Our framework accommodates coupling effects among resistors, memristors, capacitors and inductors. Copyright © 2010 John Wiley & Sons, Ltd.
40 citations
TL;DR: Tunability and input-signal amplitude limitations of the proposed circuits due to the operational restrictions of the electronic resistors are examined and PSPICE simulations confirm the validity and the practical utility ofThe proposed circuits.
Abstract: The main motivation in this paper is to draw attention to the tunability and input-signal amplitude limitations when a nonlinear device is used as a resistor. For this purpose, two first-order all-pass filters are proposed using differential difference current conveyor (DDCC), a capacitor and a resistor without element-matching restriction. These all-pass filter circuits can be made electronically tunable with electronic resistors. Tunability and input-signal amplitude limitations of the proposed circuits due to the operational restrictions of the electronic resistors are examined. PSPICE simulations confirm the validity and the practical utility of the proposed circuits. Copyright © 2010 John Wiley & Sons, Ltd.
(The main motivation in this paper is to draw attention to the tunability and input-signal amplitude limitations when a nonlinear device is used as a resistor. For this purpose, two first-order all-pass filters are proposed using differential difference current conveyor (DDCC), a capacitor and a resistor without element-matching restriction.)
TL;DR: A novel first-order all- pass filter is proposed to show advantages and new circuit producing capability of the ICDBA/C-ICDBA and an electronically tunable band-pass filter is given as an application example using the presented all-passfilter.
Abstract: In this study, new active elements called inverting current differencing buffered amplifier (ICDBA) and current-controlled ICDBA (C-ICDBA) are presented. Unlike current differencing buffered amplifier (CDBA), their voltage transfer ratio between the Z and W terminals are equal to minus one. Furthermore, CMOS implementations of the C-ICDBA and current-controlled CDBA (C-CDBA) are shown. Moreover, a novel first-order all-pass filter is proposed to show advantages and new circuit producing capability of the ICDBA/C-ICDBA. Lastly, an electronically tunable band-pass filter is given as an application example using the presented all-pass filter. The measured and simulation results are in good agreement with the theoretical ones. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: The Z Copy-Controlled Gain-Current Differencing Buffered Amplifier (ZC-CG-CDBA) is introduced in the paper and the extension of application range of the ZC- CG- CDBA compared with the conventional CDBA is referred to.
Abstract: The Z Copy-Controlled Gain-Current Differencing Buffered Amplifier (ZC-CG-CDBA) is introduced in the paper. In addition to the well-known CDBA, the input Current Differencing Unit (CDU) is modified and completed by special circuits. Analogously to the conventional CDBA, the z terminal is internally connected to the input of voltage buffer. The current gain from the difference input p, n to the output z can be controlled electronically or by an external device. In addition, an independent high-impedance output zc is available, providing difference current Ip−In. In the paper, the extension of application range of the ZC-CG-CDBA compared with the conventional CDBA is referred to. The novel circuit element is assembled from commercial integrated circuits and its principle is verified experimentally on a universal second-order filter. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: A novel wideband recursive digital integrator and differentiator is presented that is of third order and highly accurate, thus suitable for real-time applications.
Abstract: In this paper a novel wideband recursive digital integrator and differentiator is presented. The integrator is obtained by interpolating three digital integration techniques and the new differentiator is obtained by modifying its transfer function appropriately. Both the integrator and the differentiator are of third order and highly accurate, thus suitable for real-time applications. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: A detailed analysis and design procedure of the diode-clamped two- switch flyback converter operated in discontinuous-conduction mode (DCM) is presented and a comparison of power losses of the two-switch and the single-switch flyback converters is given.
Abstract: The two-switch flyback DC–DC converter is an extended version of the conventional single-switch flyback converter An additional switch and two clamping diodes serve as a simple, but an effective way to limit the switch overvoltages, which occur in the conventional single-switch flyback converter due to the ringing of the resonant circuit formed by the transformer leakage inductance and the transistor output capacitance The clamping diodes in the two-switch flyback topology clamp the maximum voltage across each switch equal to the DC input voltage This paper presents a detailed analysis and design procedure of the diode-clamped two-switch flyback converter operated in discontinuous-conduction mode (DCM) A comparison of power losses of the two-switch and the single-switch flyback converters is given The two-switch flyback converter was bread-boarded to validate the theoretical analysis Experimental results from a 20-V/30-W, 100-kHz laboratory prototype verified that the maximum switch voltage is limited to the DC input voltage Copyright © 2010 John Wiley & Sons, Ltd
TL;DR: A technique to automatically control the gate bias voltage of a bulk-driven differential pair is proposed to optimize the design tradeoff between the effective input transconductance and the input current.
Abstract: In this paper the response of a bulk-driven MOS Metal-Oxide-Semiconductor input stage over the input common-mode voltage range is discussed and experimentally evaluated. In particular, the behavior of the effective input transconductance and the input current is studied for different gate bias voltages of the input transistors. A comparison between simulated and measured results, in standard 0.35-µm CMOS Complementary Metal-Oxide-Semiconductor technology, demonstrates that the model of the MOS transistors is not sufficiently accurate for devices operating under forward bias conditions of their source-bulk pn junction. Therefore, the fabrication and the experimental evaluation of any solution based on this approach are highly recommended. A technique to automatically control the gate bias voltage of a bulk-driven differential pair is proposed to optimize the design tradeoff between the effective input transconductance and the input current. The proposed input stage was integrated as a standalone block and was also included in a 1.5-V second-order operational transconductance amplifier (OTA)-C lowpass filter. Experimental results validate the effectiveness of the approach. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: A linear voltage to current converter, based on the adapted current mirror, is proposed and its static and dynamic behaviour is presented and validated with the same technology.
Abstract: Current mirror is one of the basic building blocks of analog VLSI systems. For high-performance analog circuit applications, the accuracy and bandwidth are the most important parameters to determine the performance of the current mirror. This paper presents an efficient implementation of a CMOS current mirror suitable for low-voltage applications. This circuit combines a shunt input feedback, a regulated cascade output and a differential amplifier to achieve low input resistance, high accuracy and high output resistance. A comparison of several architectures of this scheme based on different architectures of the amplifier is presented. The comparison includes: input impedance, output impedance, accuracy, frequency response and settling time response. These circuits are validated with simulation in 0.18µm CMOS TSMC of MOSIS. In this paper, a linear voltage to current converter, based on the adapted current mirror, is proposed. Its static and dynamic behaviour is presented and validated with the same technology. Copyright © 2009 John Wiley & Sons, Ltd.
TL;DR: It is demonstrated that the derived filter structures can realize a general class of second-order current transfer functions and are general and very appropriate for integration, cascading and electronic tuning.
Abstract: A versatile family of two integrator loop filter structures using current differencing transconductance amplifiers (CDTAs) and grounded capacitors is generated. The basic filter building blocks consist of current proportional blocks, current lossless integrators and a current lossy integrator based on the use of CDTAs as the major active components. It is demonstrated that the derived filter structures can realize a general class of second-order current transfer functions. Since the resulting structures contain only CDTAs and grounded capacitors, they are general and very appropriate for integration, cascading and electronic tuning. The influences of the CDTA non-idealities are also discussed. The functionality of the resulting filters has been verified by simulation results. Copyright © 2009 John Wiley & Sons, Ltd.
TL;DR: A new circuit topology for realizing second-order current-mode quadrature oscillator is proposed, resulting in four distinct circuits that exhibit non-interactive frequency control and low THD.
Abstract: In this paper a new circuit topology for realizing second-order current-mode quadrature oscillator is proposed. Three additional circuits are further derived from it, thus resulting in four distinct circuits. Each circuit employs three differential voltage current conveyors and all grounded passive components, ideal for IC implementation. All the circuits possess high output impedance. The circuits exhibit non-interactive frequency control and low THD. The effects of non-idealities are also analyzed. PSPICE simulations using 0.5 µCMOS parameters confirm the validity and practical utility of the proposed circuits. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: A modified two-integrator-loop topology is developed to offer independent control of the pole frequency and quality factor without disturbing the passband gain and overcomes several drawbacks of the previous solutions.
Abstract: SUMMARY
A second-generation current conveyor with digitally programmable current gains is presented. A current division network with zero standby power consumption is utilized in two different ways to provide both gain and attenuation of the second-generation current conveyor's current transfer characteristics. The proposed topology overcomes several drawbacks of the previous solutions through affording a more power and area efficient solution while exhibiting relatively wider tuning range and bandwidth. A variable-gain amplifier and a two-integrator-loop filter biquad providing low-pass and band-pass responses are given as application examples. A modified two-integrator-loop topology is developed to offer independent control of the pole frequency and quality factor without disturbing the passband gain. Simulation results obtained from a standard 0.18 µm complementary metal–oxide semiconductor process are given. Copyright © 2011 John Wiley & Sons, Ltd.
TL;DR: In this article, the frequency-domain-based realization condition related to a novel non-invasive chaos control is presented for a voltage-mode buck converter, and the simulation and experiment results about the application of the chaos control to a voltagemode Buck converter are given, which confirm the feasibility of the parameter optimization method and the validity of the proposed chaos control.
Abstract: The frequency-domain-based realization condition related to a novel non-invasive chaos control is presented in this paper. According to the common piecewise-linear characteristics of PWM-controlled DC–DC converter system, a general expression for its Jacobian matrix is derived for optimizing the control parameters of the proposed non-invasive chaos control. The relevant simulation and experiment results about the application of the chaos control to a voltage-mode Buck converter are given, which confirm the feasibility of the parameter-optimization method and the validity of the proposed non-invasive chaos control. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: New pathological mirror and nullor representations of the two-output current conveyor family are given and compared with the corresponding nullator norator resistors' realizations, demonstrating the importance of the pathological representation in the generation of a family of 16 oscillator-based current mode oscillator.
Abstract: The pathological mirror and nullor representation of the two-output current conveyor family is given. New pathological mirror and nullor representations of the two-output current conveyor family are given and compared with the corresponding nullator norator resistors' realizations. Simplified representations of the two-output current conveyors based on using two single-output current conveyors are given. Two examples are given, the first example demonstrates the importance of the pathological representation in the generation of a family of 16 oscillators from a two-output current conveyor-based current mode oscillator. A second example of a current mode low-pass filter using two single-output inverting current conveyors is considered. Its simplified modeling using a single balanced output inverting current conveyor is compared with the original current mode filter and the simulation results are given. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: It is concluded that to compensate the reactive power is a simple circuit synthesis problem.
Abstract: A new generalized reactive power compensation algorithm applicable to a multi-line system under sinusoidal conditions is reviewed. This method does not require any decomposition of reactive power or non-active current. It is shown that a realization of the compensator can be obtained by means of a simple connection of reactive elements. Accordingly, it is concluded that to compensate the reactive power is a simple circuit synthesis problem. The algorithm is illustrated by means of examples. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: In this paper, several circuit design parameters, such as supply voltage, transistor size, and transistor gate voltage in the sensing circuit, are evaluated to discover the root causes of reduced sensing margin with technology scaling.
Abstract: Magnetoresistive random access memory (MRAM) is a leading candidate for future memory applications because it may provide compelling advantages by combining desirable attributes of SRAM, DRAM, and Flash. Process technology has recently scaled down to the nano-meter regime, which accordingly has resulted in lowering supply voltage, increasing short channel effect, and rapidly increasing process variation. MRAM is also affected by technology scaling, which significantly reduces the sensing margin. In this paper, several circuit design parameters, such as supply voltage, transistor size, and transistor gate voltage in the sensing circuit, are evaluated to discover the root causes of reduced sensing margin with technology scaling. The lowered supply voltage and lowered output resistance of the transistor, which occurs with technology scaling, are verified as the root causes of reduced sensing margin. It is also shown that increased process variation due to technology scaling aggravates the problem. A high supply voltage with power gating combined with optimized transistor size and gate voltage, and a power gating scheme using an IO device with an IO voltage are suggested as effective design solutions for reliably increasing the sensing margin in the presence of process variation. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: A superharmonic voltage-controlled injection-locked frequency divider, implemented using a modified Colpitts oscillator and a cross-coupled LC oscillator, is demonstrated, achieving triple-band operation by employing a novel technique that uses pin-diodes and negative power supply.
Abstract: A superharmonic voltage-controlled injection-locked frequency divider, implemented using a modified Colpitts oscillator operating at 2.5, 5 and 10 GHz and a cross-coupled LC oscillator operating at 1.25, 2.5 and 5 GHz, is demonstrated. The proposed triple-band operation is achieved by employing a novel technique that uses pin-diodes and negative power supply. The discrete dividers, built with low noise hetero-junction FETs and high-frequency SiGe BJTs, are described theoretically while their functionality is proven experimentally. Additionally, a short phase noise analysis, which is missing in the literature, is given. Phase noise, frequency range of operation, and locking range measurement results are presented. Finally, post-layout simulation results of a 5 GHz fully differential injection-locked frequency divider, implemented in a 0.25µm SiGe process are provided. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: A thorough analysis of the settling response of three-stage nested-Miller-compensated opamps, including linear and non-linear sections, is presented, which leads to a design methodology which determines the circuit requirements for desired settling time/error.
Abstract: In analog signal-processing applications, settling performance of the employed operational amplifiers (opamps) is usually of great matter. Under low-voltage environment of modern technologies where only a few transistors are allowed to be stacked, three-stage amplifiers are gaining more interest. Unfortunately, design and optimization of three-stage opamps based on settling time still suffer from lack of a comprehensive analysis of the settling behavior and closed-form relations between settling time/error and other parameters. In this paper, a thorough analysis of the settling response of three-stage nested-Miller-compensated opamps, including linear and non-linear sections, is presented. This analysis leads to a design methodology which determines the circuit requirements for desired settling time/error. Based on settling time, it allows optimizations in power consumption and area. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: Experimental results show that high MPPT accuracy and conversion efficiency can be simultaneously achieved under high frequency operation.
Abstract: A battery charger with MPPT function for low-power PV system applications is presented in this study. For effective miniaturization, the battery charger is designed with high-frequency operation. Some current-sensing techniques are studied, and their MPPT implementation is compared. A battery charging method is also designed to prolong battery lifetime without the use of battery current sensors. The operation principles and design considerations of the proposed PV charger are analyzed and discussed in detail. A laboratory prototype is implemented and tested to verify the feasibility of the proposed scheme. Experimental results show that high MPPT accuracy and conversion efficiency can be simultaneously achieved under high-frequency operation. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: A new form of Modal series is used to obtain the transient time-domain response of oscillators that is applicable to n-dimensional systems and is not dependent on the existence of a small parameter in circuit's model.
Abstract: In this paper, a new form of Modal series is used to obtain the transient time-domain response of oscillators. It is applicable to n-dimensional systems and is not dependent on the existence of a small parameter in circuit's model. In addition, it provides an approximate analytical expression for the transient response instead of numerical solutions. It is valuable since the transient response of oscillators is not frequency stationary and therefore the FFT of numerical methods may not be so useful. The Colpitts oscillator is selected as a case study and a closed-form expression for its transient response is derived which approximates the real response up to the steady state. Copyright © 2009 John Wiley & Sons, Ltd.
TL;DR: Nodal admittance matrix (NAM) expansion is used to generate a family of grounded passive component Kerwin Huelsman Newcomb (KHN) circuits, which have independent control on the selectivity factor and the radian frequency as in the original KHN.
Abstract: Nodal admittance matrix (NAM) expansion is used to generate a family of grounded passive component Kerwin Huelsman Newcomb (KHN) circuits. The generated KHN circuits have independent control on the selectivity factor and the radian frequency as in the original KHN, besides they have independent control on the gain, which is not achievable in the original KHN circuit. The NAM expansion is based on using nullor elements and voltage mirror and current mirror as well. Two types of the KHN circuit are considered, each includes four classes. For each class it is found that there are 32 different KHN circuit; therefore, there is a total of 128 circuits that belong to type-A KHN and a similar number for type-B KHN circuits. Simulation results are included to support the generation method. Copyright © 2010 John Wiley & Sons, Ltd.
TL;DR: An implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image processing algorithms, achieving high operational performance and low power consumption is presented.
Abstract: This paper demonstrates an implementation of an asynchronous cellular processor array that facilitates binary trigger-wave propagations, extensively used in various image-processing algorithms. The circuit operates in a continuous-time mode, achieving high operational performance and low-power consumption. An integrated circuit with proof-of-concept array of 24×60 cells has been fabricated in a 0.35µm three-metal CMOS process and tested. Occupying only 16×8µm2 the binary wave-propagation cell is designed to be used as a co-processor in general-purpose processor-per-pixel arrays intended for focal-plane image processing. The results of global operations such as object reconstruction and hole filling are presented. Copyright © 2010 John Wiley & Sons, Ltd.