Showing papers in "Journal of microelectronics and electronic packaging in 2018"
TL;DR: In this paper, the first stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere was reported, achieving a more than 7-fold increase in circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.
Abstract: This work describes recent progress in the design, processing, upscaling, and testing of 500°C durable two-level interconnect 4H-SiC JFET IC technology undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for 1 year (8760 hours) at 500°C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500°C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016.
25 citations
TL;DR: In this article, the design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated.
Abstract: The design, materials, process, and fabrication of a heterogeneous integration of four chips by a fan-out panel-level packaging (FOPLP) method are investigated in this study. Emphasis is placed on (1) the application of a dry-film epoxy molding compound for molding the chips and (2) the application of a special assembly process called uni-substrate-integrated package for fabricating the redistribution layers (RDLs) of the FOPLP. The Ajinomoto build-up film is used as the dielectric of the RDLs and is built up by the semiadditive process. Electroless Cu is used to make the seed layer, laser direct imaging is used for opening the photoresist, and printed circuit board (PCB) Cu plating is used for making the conductor wiring of the RDLs. The panel dimensions are 508 × 508 mm. The package dimensions of the FOPLP are 10 × 10 mm. The large chip size and the small chip sizes are, respectively, 5 × 5 mm and 3 × 3 mm. The uniqueness of this study is that all the processes are carried out by using the PCB ...
18 citations
TL;DR: In this article, the authors proposed enhancements on power electronic systems with reduced chip area and miniaturized passive components are subject of several research activities in academics and industry. To realize such fu...
Abstract: Enhancements on power electronic systems with reduced chip area and miniaturized passive components are subject of several research activities in academics and industry. To realize such fu...
17 citations
TL;DR: In this article, the reliability performance of a fan-out wafer-level SiP or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 × 3 mm), and three fans was investigated.
Abstract: In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three ...
15 citations
TL;DR: This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integrati...
Abstract: This article demonstrates a next-generation high-performance 3D packaging technology with smaller form factor, excellent electrical performance, and reliability for heterogeneous integrati...
15 citations
TL;DR: In this paper, the authors present experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars pressure.
Abstract: This paper presents experimental results of a prototype high temperature co-fired ceramic (HTCC) package with Au/Pt metallization in a three-phase harsh environment test that culminated with 60-day demonstration in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars pressure. The prototype package is based on a previously developed and reported HTCC package successfully tested with multiple analog and digital silicon carbide (SiC) high temperatures semiconductor integrated circuits (ICs) at NASA Glenn Research Center in 500 degrees Centigrade Earth air ambient for over ten thousand hours, and short-term tested at temperatures above 800 degrees Centigrade. The three-phase harsh environment test started with 48 hours in 465 degrees Centigrade Earth air, followed by 48 hours in 465 degrees Centigrade nitrogen at 90-bar pressure and 1400 hours in simulated Venus surface environment of 465 degrees Centigrade with corrosive atmosphere at 90 bars. Initial analytical results of the package materials and surfaces after exposure to the Venus environment are discussed to assess the stability of the packaging materials in the tested environments. The test in a simulated Venus environment was implemented in the NASA Glenn Extreme Environment Rig (GEER). The results of this study suggest that an effective encapsulation of areas of surface metallization and vicinities may help to improve electrical performance of a HTCC alumina packaging system in Venus environment.
6 citations
TL;DR: In this article, the authors used finite element analysis software to perform the required reliability analysis in a shorter time period and save valuable resources and reduce the cost of computational analysis of new products.
Abstract: Reliability is of a concern when designing new products Extensive set of reliability tests are performed before a product is ready to be shipped for use Drop testing, thermal cycling, power cycling, etc are some of the tests used to assess the reliability of new electronic products However, performing experimental study of every new design is costly and time consuming Computational tools (such as finite element analysis software) are often employed to perform the required reliability analysis in a shorter time period and save valuable resources One of the challenges of performing computational analysis is obtaining accurate material property data to be used for building accurate models Extensive set of material characterization work needs to be carried out before an accurate model can be developed For example, for a new printed circuit board (PCB), the bulk properties are often characterized by equipment such as thermomechanical analyzer and tensile testing machines to obtain the bulk properties t
2 citations
TL;DR: In this article, the material properties of highly filled systems of reactive epoxy molding compounds (EMC) depen-ture properties are investigated for compressive molding with liquid encapsulants.
Abstract: Compression molding with liquid encapsulants is a crucial process in microelectronic packaging. Material properties of highly filled systems of reactive epoxy molding compounds (EMC) depen...
2 citations
TL;DR: In this paper, the authors provide results of numerous in-house and field testing, comparing printed line width control, edge definition, and improved conductivity of printed polymer Ag co...
Abstract: A major obstacle in screen printing conductive low temperature curing polymer thick film (PTF) pastes onto common flexible PET substrate materials is the substantial spread of the pastes beyond the designed line width after printing. Industry observation and controlled testing have shown this spread can be as much as 80% over the circuit design's intended line width. This phenomenon prevents designers from increasing circuit density and/or reducing circuit real estate without incorporating other, more involved and higher cost patterning methods. In many cases, flexible circuit fabricators, desiring more accurate high definition circuit elements, may have to subcontract parts out of house in order to incorporate alternate patterning methods. In-turn this subcontracting leads to a loss of control of both cost and lead time. This paper will provide results of numerous in-house and field testing, comparing printed line width control, edge definition, and improved conductivity of printed polymer Ag co...
2 citations
TL;DR: In this article, stretchable silver inks are formulated for wide traces, typically larger than 2.5 cm. But they are not suitable for printed flexible electronics. And they cannot be used for flexible electronics, such as printed flexible electronic circuits.
Abstract: The lightweight and bendable features of printed flexible electronics are increasingly attractive. Currently stretchable silver inks are formulated for wide traces, typically larger than 2...
2 citations
TL;DR: In this paper, low-impedance microcoaxial cables have been developed to supply power to microchips, which are enabled by a very thin dielectric compared with a conventional...
Abstract: Low-impedance microcoaxial cables have been developed to supply power to microchips. These uniquely low-inductance cables are enabled by a very thin dielectric compared with a conventional...
TL;DR: The Surface Evolver software package is used in combination with analytical models, to analyze the behavior of various connection configurations with respect to variations in printed solder volume, and calculates the equilibrium shape of the solder surface over the connected set of pads and examines how control of joint height is affected by the number, size and geometry of auxiliary pad configurations.
Abstract: The cost of optoelectronic assemblies is significantly higher than that of electronic assemblies due in large part to the method of assembly. A typical computer circuit board is built by screen printing solder paste onto a printed wiring board, placing components on the board at rates of several thousand per hour, and then reflowing the solder paste in a conveyor oven. By contrast, optoelectronic assemblies are built up in a sequential process in which epoxy is dispensed for a single component, which is placed and held in position until the epoxy is cured. Many minutes are required to build an optoelectronic assembly, such as a laser module, by this approach, also the precision robotic placement tool needed for this process costs in excess of a million dollars. The demand for all types of optoelectronic components in communications, computing, automotive, medical and aerospace applications is great, but the high cost of manufacture is constraining growth, so clearly a better method of assembly is...
TL;DR: The need for compactness and efficiency of processing devices has kept increasing rapidly over the past few years as mentioned in this paper, and this need has driven the dice to be stacked one above the other.
Abstract: The need for compactness and efficiency of processing devices has kept increasing rapidly over the past few years. This need for compactness has driven the dice to be stacked one above the...
TL;DR: In this paper, double-side or 3-dimensional integration of high-precision and high-performance bandpass and lowpass filters that are interconnected with through-vias was designed and demonstrated on 100-micron sensors.
Abstract: Double-side or 3-D integration of high-precision and high-performance bandpass and lowpass filters that are interconnected with through-vias were designed and demonstrated on 100-micron th...
TL;DR: In this article, the authors derived the effective roughness dielectric (ERD) parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectrics and foil.
Abstract: Effective roughness dielectric (ERD) is a homogeneous lossy dielectric layer of certain thickness with effective (averaged) dielectric parameters. The ERD layer is used to model copper foil roughness in printed circuit board interconnects by being placed on a smooth conductor surface to substitute an inhomogeneous transition layer between a conductor and laminate substrate dielectric. This work derives the ERD parameters based on the understanding that there is a gradual variation of concentration of metallic inclusions in the transition layer between the dielectric and foil. The gradual variation can be structured as thin layers that are obtained using the equivalent capacitance approach. The concentration profile is extracted from scanning electron microscopy or high-resolution optical microscopy. As the concentration of metallic particles increases along the axis normal to the laminate dielectric and foil boundary, two regions can be discerned: an insulating (prepercolation) region and a conducting (pe...
TL;DR: In this paper, the authors introduce and evaluate a new end-of-aisle cooling design which consists of three cooling configurations: passive heat exchanger with rack fan walls, active heat exchander with fans, and active HX coupled with fans.
Abstract: The objective of this work is to introduce and evaluate a new end-of-aisle cooling design which consists of three cooling configurations. The key objectives of close-coupled cooling are to enable controlled cooling of information technology (IT) equipment, flexible and modular design, and the containment of hot air exhaust from the cold air. The thermal performance of the proposed solution is evaluated using computational fluid dynamics modeling. A computational model of a small size data center room has been developed. The room is modeled to be a hot aisle containment setup, i.e., the hot air exhaust exiting for each row is contained and directed within a specific volume. The cold aisle is separated from the hot aisle by means of banks of heat exchangers (HXs) placed on either side of the containment aisle. Based on the placement of rack fans, the design is divided into three sub-designs—Case 1: passive HXs with rack fan walls; Case 2: active HXs (coupled with fans) with rack fan walls; Case 3: active HX...
TL;DR: In this article, a planar printed circuit board (PCB) sensor is used to measure the electrical conductivity of a mass of sand and 125 mL of distilled water, and a line is fitted to a plot of the three data points, the slope of that line represents an estimate of the expected increase in electrical conduc...
Abstract: The most common type of electronic packaging, the printed circuit board (PCB), is also useful for realizing low-cost environmental sensors for applications such as measuring increases in the salinity of water. Salts adhering to relocated coastal sand can leach into and contaminate freshwater bodies. When adjusted for temperature, the presence of the leached salt in freshwater can be detected by measuring the accompanying increase in electrical conductivity (EC) of the resulting aqueous solution. To estimate the increase in EC from salt leaching from a mass of sand, a technique was developed based on using a low-cost planar PCB sensor, 2 g of the sand, and 125 mL of distilled water. Using the sensor, the electrical conductance is measured in the distilled water, in the distilled water with 1 g of added sand, and in the distilled water with 2 g of added sand. After a line is fitted to a plot of the three data points, the slope of that line represents an estimate of the expected increase in electrical conduc...
TL;DR: In this article, a new technology based on mixing of standard alloy SnCu in form of solder paste with copper paste was presented, which allows the production of solder joints with higher standoff consisting of intermetallic compounds.
Abstract: New technology based on mixing of standard alloy SnCu in form of solder paste with copper paste was presented. This technology allows the production of solder joints with higher standoff consisting of intermetallic compounds. Such solder joints were qualified for high temperature applications by investigation of thermal stability of overlapped solder joints. For this purpose a special test bench for the investigation of remelting temperature up to 300°C was developed.
TL;DR: In this paper, a new light emitting diode (LED) indoor lighting module with high color rendering index greater than 95 was developed for developing a new LED indoor lighting system, where a heat sink is designed to absorb and transfer heat from the LED module.
Abstract: This research is for developing a new light emitting diode (LED) indoor lighting module with high color rendering index greater than 95. When the LED is operated, electrical energy is generated and heat is released. The failing of heat dispersal degrades the performance and decreases the operating life. To manage the thermal problem effectively, several approaches have been tested in this research study. A heat sink is designed to absorb and transfer heat from the LED module. To analyze the heat flow and thermal stress of the designed LED products effectively, hexahedral mesh generation has been implemented. Heat transfer analysis was performed to find an optimal conductive material. The outcomes of this research study suggest the best material for LED products and show the result of thermal transfer simulation.
TL;DR: In this paper, the microstructure and dielectric properties of Al2O3/K-B-Si borosilicate, together with the effects of Ca doping, were investigated.
Abstract: Al2O3/K2O3–B2O3–SiO2 low temperature cofired ceramics (LTCC) dielectric materials doped with CaCO3 were prepared by using a solid-state reaction. The microstructure and dielectric properties of Al2O3/K–B–Si borosilicate, together with the effects of Ca doping, were investigated. A new material system candidate of Al2O3/KBSiO borosilicate doped by Ca was achieved after sintering at 880°C, which presents an optimized performance on dielectric properties with a permittivity ϵr < 8 and dielectric loss tan δ ≤ 0.002 and excellent stabilities across very broad frequency and temperature ranges. Most importantly, the initial results have also indicated that the new dielectric composite material is well compatible with the existing LTCC process, suggesting a considerable potential for practical LTCC applications.
TL;DR: In this article, progress made in the area of thermal interface materials (TIMs) and system cooling solutions are presented and the focus is on the evolution of TIMs and cooli
Abstract: The ever increasing demand for fast computing has led to heterogeneous integration of packages as can be seen in the latest Xeon family segments in the market Microprocessors are now adjacent to memory chips, transceivers, field-programmable gate arrays, and even other microprocessors within a single substrate These complex designs have instigated an increase in cooling demand for microprocessors, and hence, there has been an increased focus within the semiconductor industry on developing advance thermal solutions From the packaging level, thermal interface materials (TIMs) play a key role in thermally connecting various components within the package and helps reduce the thermal resistance between the die surfaces and integrated heat spreaders From the system level, cooling technology is critical to attain the desired overall thermal dissipation and performance In this review, progress made in the area of TIMs and system cooling solutions are presented The focus is on the evolution of TIMs and cooli