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Journal ArticleDOI

A 1.5 GHz highly linear CMOS downconversion mixer

TLDR
In this paper, a CMOS mixer topology for use in highly integrated downconversion receivers is presented, which is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch.
Abstract
A CMOS mixer topology for use in highly integrated downconversion receivers is presented. The mixing is based on the modulation of nMOS transistors in the triode region which renders an excellent linearity independent of mismatch. With two extra capacitors added to the classical cross-coupled MOSFET-C lowpass filter structure, GHz signals can be processed while only a low-frequency opamp is required as output amplifier. The downconversion mixer has an input bandwidth of 1.5 GHz. The measured third-order intercept point (IP3) of 45.2 dBm demonstrates the high linearity. The mixer has been implemented in a 1.2 /spl mu/m CMOS process. It takes up 1 mm/sup 2/ of total chip area and its power consumption is 1.3 mW from a single 5 V power supply. >

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Citations
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Journal ArticleDOI

A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topology

TL;DR: In this paper, an analog receiver front end chip realized in a 0.7 /spl mu/m CMOS technology is presented, which achieves a phase accuracy of less than 0.3/spl deg/ in a large passband around 900 MHz without requiring any external component or any tuning or trimming.
Journal ArticleDOI

A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiver

TL;DR: An integrated low-noise amplifier and down-conversion mixer operating at 1 GHz has been fabricated for the first time in 1 /spl mu/m CMOS as discussed by the authors, where the overall conversion gain is almost 20 dB, the double-sideband noise figure is 3.2 dB, and the IIP3 is +8 dBm.
Journal ArticleDOI

A CMOS passive mixer with low flicker noise for low-power direct-conversion receiver

TL;DR: In this paper, a single-balanced passive mixer is proposed to mitigate the critical flicker noise problem that is frequently encountered in constituting direct-conversion receivers, which achieves an ultralow flicker-noise corner of 45 kHz with 6 dB more gain and much lower power and area consumption than the double-balanced counterpart.
Journal ArticleDOI

Low voltage performance of a microwave CMOS Gilbert cell mixer

TL;DR: In this paper, the low voltage operation of a doubly balanced Gilbert mixer fabricated in a 0.8/spl mu/m CMOS process and operating as both a down-converter and an up-converster was demonstrated.
Patent

Dual mode tuner for co-existing digital and analog television signals

TL;DR: In this paper, a dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed, and a precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal.
References
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Journal ArticleDOI

A 20-V four-quadrant CMOS analog multiplier

TL;DR: A novel technique is presented for performing the analog multiplication in CMOS technology by linearizing the source-coupled circuit and introducing the folded CMOS GSTC.
Journal ArticleDOI

An MOS four-quadrant analog multiplier using simple two-input squaring circuits with source followers

TL;DR: In this paper, an MOS four-quadrant analog multiplier is described based on the square-law dependence of the MOS-transistor drain current on the gate-to-source voltage in the saturation region.
Proceedings Article

A Highly Linear 1-GHz CMOS Downconversion Mixer

TL;DR: In this article, a linear, closed loop CMOS architecture is demonstrated for the mixing of RF waveforms to baseband as sampled-data signals, and the measured third-order intercept lies at +27 dBm of input power.
Journal ArticleDOI

CMOS RF circuits for data communications applications

TL;DR: In this article, the authors describe the development of two analog CMOS circuits operating at RF frequencies with applications to data communications, one is a four-quadrant analog multiplier which exhibits a 100MHz bandwidth with a measured linearity error of 0.7% for X and Y inputs.
Proceedings ArticleDOI

An integrated Si bipolar RF transceiver for a zero IF 900 MHz GSM digital mobile radio frontend of a hand portable phone

TL;DR: In this article, a single-chip solution for a GSM (Group Special Mobile) 900-MHz RF TX quadrature modulator and RX quadratures demodulator was designed and fabricated in a 9-GHz silicon bipolar technology.
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