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Proceedings ArticleDOI

A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing

TLDR
In this paper , a 0.6 V dynamic biased, body driven Strong Arm latch is presented, which exploits a charge pump based dynamic biasing configuration that boosts the effective supply headroom.
Abstract
In this paper a novel 0.6 V dynamic biased, body driven Strong Arm latch is presented. The proposed topology exploits a charge pump based dynamic biasing configuration that boosts the effective supply headroom. In addition, the body terminals are used to drive the input pair while the gates are driven by the clock signal to allow for the removal of the tail transistor, resulting in larger peak currents and smaller parasitic capacitances. This reduces power consumption and delay. Moreover, the body driven approach enables rail-to-rail input common mode range (ICMR). As a result, the proposed topology is capable of high-speed operation (up to 2.5 GHz) despite the low supply voltage. At 2.5 GHz the comparator shows a competitive energy-delay product (EDP) of 2.98 fJ/GHz.

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Proceedings ArticleDOI

A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V

TL;DR: Clocked regenerative comparators, which use positive feedback of a latch to force a fast decision, are used for many applications and are designed to extract every 4th bit of a 40Gb/s data stream.
Proceedings ArticleDOI

A low-offset latched comparator using zero-static power dynamic offset cancellation technique

TL;DR: In this article, a low-offset latched comparator using new dynamic offset cancellation technique is proposed, which achieves low offset voltage without pre-amplifier and quiescent current.
Proceedings ArticleDOI

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

TL;DR: The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work, and the proposed offset calibration technique improves the offset voltage from 11.6mV to 533μV at 1 sigma.
Journal ArticleDOI

A Low-Voltage and Low-Power Adaptive Switched-Current Sigma–Delta ADC for Bio-Acquisition Microsystems

TL;DR: An ultralow-voltage and low-power adaptive sigma-delta analog-to-digital converter (SDADC) with a 10-bit dynamic range for bio-microsystem applications is presented and it is revealed that the dynamic range is still over 60 dB without degrading by digital circuits.
Proceedings Article

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