Proceedings ArticleDOI
A 34% PAE, 18.6dBm 42–45GHz stacked power amplifier in 45nm SOI CMOS
Amir Agah,Hayg Dabag,Bassel Hanafi,Peter M. Asbeck,Lawrence E. Larson,James F. Buckwalter +5 more
- pp 57-60
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TLDR
In this article, a two-stack 42-45GHz power amplifier is implemented in 45nm SOI CMOS, where transistor stacking allows increased drain biasing to increase output power.Abstract:
A two-stack 42–45GHz power amplifier is implemented in 45nm SOI CMOS. Transistor stacking allows increased drain biasing to increase output power. Additionally, shunt inter-stage matching is used and improves PAE by more than 6%. This amplifier exhibits 18.6dBm saturated output power, with peak power gain of 9.5dB. It occupies 0.3mm2 including pads while achieving a peak PAE of 34%. The PAE remains above 30% from 42 to 45GHz.read more
Citations
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Journal ArticleDOI
Analysis and Design of Stacked-FET Millimeter-Wave Power Amplifiers
TL;DR: In this paper, stacked field effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors.
Journal ArticleDOI
High-Power High-Efficiency Class-E-Like Stacked mmWave PAs in SOI and Bulk CMOS: Theory and Implementation
TL;DR: The two-Stacked PA exhibits the highest PAE reported for CMOS mmWave PAs, and the four-stacked PA achieves the highest output power from a fully integrated CMOSmmWave PA including those that employ power combining, despite the poor ON-resistance of the 65-nm low-power nMOS devices.
Journal ArticleDOI
Performance Limits, Design and Implementation of mm-Wave SiGe HBT Class-E and Stacked Class-E Power Amplifiers
Kunal Datta,Hossein Hashemi +1 more
TL;DR: High power, highly efficient, switching power amplifier unit cells presented in this paper can facilitate realization of efficient Watt-level mm-wave digital polar transmitters.
Journal ArticleDOI
Analysis and Design of Millimeter-Wave Power Amplifier Using Stacked-FET Structure
Young-Min Kim,Youngwoo Kwon +1 more
TL;DR: In this paper, a new analysis methodology for millimeter-wave stacked-FET power amplifier design is proposed with a focus on the output power improvement by adjusting the complex load-admittance of each stacked-transistor.
Journal ArticleDOI
A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters
Andreea Balteanu,I. Sarkas,E. Dacquay,A. Tomkins,Gabriel M. Rebeiz,Peter M. Asbeck,Sorin P. Voinigescu +6 more
TL;DR: A high-efficiency, large output-power, mm-wave digital transmitter architecture is proposed for high data rate m-ary QAM transmission and its suitability as a large-swing NRZ modulator driver in fiberoptic links is demonstrated.
References
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Proceedings ArticleDOI
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TL;DR: A new device configuration is presented: the High-Voltage/High-Power device (HiVP), which can dramatically improve the power and decrease the complexity of designing power amplifiers, leading to low cost and higher power.
Proceedings ArticleDOI
A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOS
TL;DR: A CMOS PA capable of delivering 13dBm OP1dB for a 3Gb/s QPSK signal and meeting the requirements of nearly omni-directional links is presented.
Journal ArticleDOI
60 GHz CMOS Amplifiers Using Transformer-Coupling and Artificial Dielectric Differential Transmission Lines for Compact Design
TL;DR: On-chip transformers combine bias, stability and input/interstage matching networks to enable compact designs and achieved a peak gain of 25 dB with 8 dB of gain variation in the variable-gain amplifier.