Journal ArticleDOI
A 4-Mbit DRAM with trench-transistor cell
Ashwin H. Shah,Chu-Ping Wang,R.H. Womack,James D. Gallia,Hisashi Shichijo,H.E. Davis,M. Elahy,Sanjay K. Banerjee,Gordon P. Pollack,William F. Richardson,D.M. Bordelon,Satwinder Malhi,C.J. Pilch,B. Tran,Pallab K. Chatterjee +14 more
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TLDR
An experimental 5V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches as mentioned in this paper.Abstract:
An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.read more
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Patent
Magnetic resonance imaging system
TL;DR: In this article, a magnetic resonance imaging system includes a magnetic field applying section for applying a static field, gradient field pulses and an RF field to an object to be examined, a signal detecting section, including a homogeneous coil and a plurality of surface coils arranged to surround a desired region of the object, for detecting magnetic resonance signals from the object through the homogeneous coils and the surface coils, and an image data processing section for obtaining an image of the desired region by synthesizing image data based on the magnetic resonance signal respectively detected by the surface coil upon weighting/adding processing
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Memory cell having a vertical transistor with buried source/drain and dual gates
TL;DR: In this article, a memory cell for a dynamic random access memory (DRAM) is constructed on semiconductor pillars on buried bit lines, and split gates are interposed between and shared between adjacent pillars for gating the transistors therein.
Patent
4 F2 folded bit line dram cell structure having buried bit and word lines
TL;DR: In this article, a memory cell structure for a folded bit line memory array of a dynamic random access memory device includes buried bit and word lines, with the access transistors being formed as a vertical structure on the bit lines.
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Low temperature silicon wafer bond process with bulk material bond strength
TL;DR: In this paper, a method for bonding one semiconductor surface to another is presented, where the semiconductor surfaces are annealed with an energy source wherein energy is confined to the surfaces.
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High density flash memory
Leonard Forbes,Wendell P. Noble +1 more
TL;DR: In this paper, a memory cell array includes densely packed memory cells, each cell having a semiconductor pillar providing shared source/drain regions for two vertical floating gate transistors that have individual floating and control gates distributed on opposing sides of the pillar.
References
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Proceedings ArticleDOI
A trench transistor cross-point DRAM cell
William F. Richardson,D.M. Bordelon,Gordon P. Pollack,Ashwin H. Shah,Satwinder Malhi,Hisashi Shichijo,Sanjay K. Banerjee,M. Elahy,R.H. Womack,Chu-Ping Wang,James D. Gallia,H.E. Davis,Pallab K. Chatterjee +12 more
TL;DR: In this article, a 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described, and its fabrication and characterization is discussed.
Proceedings ArticleDOI
A 4Mb DRAM with cross point trench transistor cell
Ashwin H. Shah,Chu-Ping Wang,R.H. Womack,J. Gallia,Hisashi Shichijo,H.E. Davis,M. Elahy,Sanjay K. Banerjee,Gordon P. Pollack,William F. Richardson,D. Bordelon,Satwinder Malhi,C.J. Pilch,Bao Tran,Pallab K. Chatterjee +14 more
TL;DR: In this article, the authors describe the design of a 9.8mm×10.2mm 1MW×4b DRAM fabricated in a 1μm double-level metal CMOS technology featuring trench-transistor cells measuring 9μm2.
Proceedings ArticleDOI
A corrugated capacitor cell (CCC) for megabit dynamic MOS memories
TL;DR: In this article, a new dRAM cell named "Corrugated Capacitor Cell" (CCC) has been successfully developed based on the one-device cell concept, characterized by an etched-moat storage-capacitor extended into the substrate, resulting in an almost independent increase in storage capacitance without cell size enlargement.
Proceedings ArticleDOI
An isolation-merged vertical capacitor cell for large capacity DRAM
TL;DR: In this article, an isolation-merged vertical capacitance (IVEC) cell is described with emphasis on its scalability, simulated device characteristics and experimentally obtained capacitor oxide breakdown voltage.