Proceedings ArticleDOI
A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation
Yuta Yamato,Tomokazu Yoneda,Kazumi Hatayama,Michiko Inoue +3 more
- pp 1-8
Reads0
Chats0
TLDR
This paper addresses the issue of vulnerability to IR-drop-induced yield loss in nano-scale designs with a novel per-cell dynamic IR- drop estimation method that achieves both high accuracy and high time-efficiency.Abstract:
In return for increased operating frequency and reduced supply voltage in nano-scale designs, their vulnerability to IR-drop-induced yield loss grew increasingly apparent. Therefore, it is necessary to consider delay increase effect due to IR-drop during at-speed scan testing. However, it consumes significant amounts of time for precise IR-drop analysis. This paper addresses this issue with a novel per-cell dynamic IR-drop estimation method. Instead of performing time-consuming IR-drop analysis for each pattern one by one, the proposed method uses global cycle average power profile for each pattern and dynamic IR-drop profiles for a few representative patterns, thus total computation time is effectively reduced. Experimental results on benchmark circuits demonstrate that the proposed method achieves both high accuracy and high time-efficiency.read more
Citations
More filters
Proceedings ArticleDOI
Machine-learning-based dynamic IR drop prediction for ECO
TL;DR: This work trains a machine learning model, based on data before ECO, and predicts IR drop after ECO to provide a fast IR drop prediction to speedup ECO and proposes to build regional models for cell instances near IR drop violations.
Proceedings ArticleDOI
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network.
TL;DR: This work develops a fast dynamic IR drop estimation technique, named PowerNet, based on a convolutional neural network (CNN), which can handle both vector-based and vectorless IR analyses and achieves a 30× speedup compared to an accurate IR drop commercial tool.
Proceedings ArticleDOI
IR drop prediction of ECO-revised circuits using machine learning
Shih-Yao Lin,Yen-Chun Fang,Yu-Ching Li,Yu-Cheng Liu,Tsung-Shan Yang,Shang-Chien Lin,Chien-Mo Li,Eric Jia-Wei Fang +7 more
TL;DR: This work proposes a machine learning technique to build an IR drop prediction model based on circuits before ECO (engineer change order) revision, which can be used to predict the IR drop of the revised circuit after revision.
Journal ArticleDOI
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill
TL;DR: This paper quantifies, for the first time, the impact of thermal emergencies on small-delay defects (SDDs) and provides a solution to mitigate them and demonstrates that the new method can significantly reduce the number of over-detections of SDDs.
Proceedings ArticleDOI
PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network
TL;DR: In this paper, the authors developed a fast dynamic IR drop estimation technique, named PowerNet, based on a convolutional neural network (CNN), which can handle both vector-based and vectorless IR analyses.
References
More filters
Proceedings ArticleDOI
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs
TL;DR: Experimental results presented for benchmark and industrial circuits demonstrate the effectiveness of the proposed method called Preferred Fill to reduce average and peak power dissipation during capture cycles of launch off capture delay fault tests.
Proceedings ArticleDOI
An analysis of power reduction techniques in scan testing
TL;DR: A scheme for reducing power is presented and analysis results on an industrial design are provided and it is shown that circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption.
Proceedings ArticleDOI
On low-capture-power test generation for scan testing
TL;DR: Experimental results show the effectiveness of the novel low-capture-power X-filling method in reducing capture power dissipation without any impact on area, timing, and fault coverage.
Proceedings ArticleDOI
Impact of multiple-detect test patterns on product quality
Brady Benware,C. Schuermyer,Nagesh Tamarapalli,Kun-Han Tsai,S. Ranganathan,R. Madge,Janusz Rajski,P. Krishnamurthy +7 more
TL;DR: An ATPG tool is introduced that generates multiple-detect test patterns while maximizing the coverage of node-to-node bridging defects, and the experimental results from the project show that it demonstrates its robustness and adaptability.
Proceedings ArticleDOI
ATPG for heat dissipation minimization during test application
TL;DR: A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds.