Journal ArticleDOI
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
Sari Onaissi,Farid N. Najm +1 more
Reads0
Chats0
TLDR
This work proposes a linear-time approach for STA which covers all process corners in a single pass and provides estimates of the worst case circuit delay and slew.Abstract:
Manufacturing process variations lead to circuit timing variability and a corresponding timing yield loss. Traditional corner analysis consists of checking all process corners (combinations of process parameter extremes) to make sure that circuit timing constraints are met at all corners, typically by running static timing analysis (STA) at every corner. This approach is becoming too expensive due to the increase in the number of corners with modern processes. As an alternative, we propose a linear-time approach for STA which covers all process corners in a single pass. Our technique assumes a linear dependence of delays and slews on process parameters and provides estimates of the worst case circuit delay and slew. It exhibits high accuracy in practice, and if the circuit has gates and relevant process parameters, the complexity of the algorithm is O(mn).read more
Citations
More filters
Proceedings ArticleDOI
PSTA-based branch and bound approach to the silicon speedpath isolation problem
TL;DR: This work proposes using characterized, pre-silicon, variational timing models to identify speedpaths that can best explain the observed delays from silicon measurements, and shows that this is achieved in a very efficient manner.
Proceedings ArticleDOI
"Unobserved Corner" Prediction: Reducing Timing Analysis Effort for Faster Design Convergence in Advanced-Node Design
TL;DR: A data-driven approach is investigated, based on multivariate linear regression, to predict the timing analysis at unobserved corners from analysis results at observed corners, which indicates that timing results for a given path at different corners will have strong correlations, if only as a consequence of physics of devices and interconnects.
Proceedings ArticleDOI
A fast approach for static timing analysis covering all PVT corners
TL;DR: In this article, the authors present an alternative method for performing fast and accurate hold timing analysis which covers all corners, and combine the results of the full and partial runs to find the worst-case hold slacks over all corners.
Proceedings ArticleDOI
A unified multi-corner multi-mode static timing analysis engine
TL;DR: A unified multi-corner multi-mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits is proposed.
Proceedings ArticleDOI
Efficient block-based parameterized timing analysis covering all potentially critical paths
TL;DR: This work proposes an efficient block-based parameterized timing analysis technique that can accurately capture circuit delay at every point in the parameter space, by reporting all paths that can become critical.
References
More filters
Proceedings ArticleDOI
First-order incremental block-based statistical timing analysis
TL;DR: In this article, a canonical first order delay model is proposed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form and the sensitivities of all timing quantities to each of the sources of variation are available.
Proceedings ArticleDOI
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
TL;DR: An efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay while incorporating the effects of spatial correlations of intra-die parametervariations, using a method based on principal component analysis.
Journal ArticleDOI
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates
J. Qian,S. Pullela,L. Pillage +2 more
TL;DR: An extension of the effective capacitance equation is proposed that captures the complete waveform response accurately, with a two-piece gate-output-waveform approximation, for the "effective load capacitance" of a pc interconnect.
Proceedings ArticleDOI
Statistical timing for parametric yield prediction of digital integrated circuits
TL;DR: Three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits are proposed and results in the face of statistical temperature and Vdd variations are presented.