Book ChapterDOI
A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator
Gudlavalleti Rajahari,Gudlavalleti Rajahari,Yashu Anand Varshney,Yashu Anand Varshney,Subash Chandra Bose,Subash Chandra Bose +5 more
- pp 10-18
TLDR
The proposed design methodology linearizes the Ibias-Vcontrol characteristic and ensures the CSTs to operate in saturation region during switching and consequently enhances the tuning range without additional circuitry.Abstract:
This paper presents a novel design methodology of a CMOS current starved ring Voltage Controlled Oscillator (VCO) for wide tuning range and high linearity. The f-V tuning characteristic of the ring VCO depends on the current-voltage (Ibias-Vcontrol) characteristic of the replica bias and region of operation of current sources/sinks transistors (CSTs). The proposed design methodology linearizes the Ibias-Vcontrol characteristic and ensures the CSTs to operate in saturation region during switching and consequently enhances the tuning range without additional circuitry. The design is implemented in UMC 0.18 μm CMOS technology at 1.8 V supply voltage. The overall circuit consumes 260 μW power at 404.5 MHz, has a wide tuning range of 66 MHz to 875 MHz having 94.5% tuning linearity.read more
Citations
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Proceedings ArticleDOI
Analysis and design of current starved ring VCO
TL;DR: In this paper, the authors focus on the analysis and design of a current starved voltage controlled ring oscillator and analyze the effect of delay time, phase noise, layout area, and technology on the frequency of oscillation at various power supplies and control voltages.
Proceedings ArticleDOI
Design of Improved Performance Voltage Controlled Ring Oscillator
TL;DR: Simulation results reveal the better performance of the proposed design as compared to existing current staved ring VCO in terms of oscillation frequency and power consumption.
Proceedings ArticleDOI
Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process
Chandra Shekhar,S. Qureshi +1 more
TL;DR: This paper presents a low power 5-stage current starved voltage controlled oscillator, designed at 50 MHz, which exhibits a phase noise of -101.9 dBc/Hz at 1 MHz offset from 50 MHz carrier frequency.
Proceedings ArticleDOI
Design and analysis of improved performance ring VCO based on differential pair configuration
TL;DR: In this article, an improved performance CMOS voltage controlled ring oscillator based on single ended differential pair configuration is presented. And the performance parameters of VCO like frequency, tuning range and power dissipation are also analyzed.
Journal ArticleDOI
Comparative Study and Design of Current Starved Ring Oscillators in 16 nm Technology
TL;DR: Simulation results demonstrate that two newly proposed CSRO architectures using one NMOS sink or one PMOS source have similar optimum results in terms of PDP and PNBP as the existing CSRO using an output switch scheme, but with an advantage of lower area requirement.
References
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Book
Design of Analog CMOS Integrated Circuits
TL;DR: The analysis and design techniques of CMOS integrated circuits that practicing engineers need to master to succeed can be found in this article, where the authors describe the thought process behind each circuit topology, but also consider the rationale behind each modification.
Journal ArticleDOI
A study of oscillator jitter due to supply and substrate noise
Frank Herzel,Behzad Razavi +1 more
TL;DR: In this paper, the timing jitter of single-ended and differential CMOS ring oscillators due to supply and substrate noise was investigated and the concept of frequency modulation was applied to derive relationships that express different types of jitter in terms of the sensitivity of the oscillation frequency to the supply or substrate voltage.
Journal ArticleDOI
A 30-MHz low-jitter high-linearity CMOS voltage-controlled oscillator
M.H. Wakayama,Asad A. Abidi +1 more
TL;DR: A fully monolithic voltage-controlled oscillator (VCO) with an on-chip timing capacitor and a maximum oscillation frequency of 30 MHz is reported, using a novel on- chip servo loop.
Journal ArticleDOI
Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study
TL;DR: A novel flow for parasitic and process-variation aware design of radio-frequency integrated circuits (RFICs) and the first work focussed on a current starved VCO in which the combined effect of parasitics and process variations has been considered is presented.
Journal ArticleDOI
A 0.5-GHz to 2.5-GHz PLL With Fully Differential Supply Regulated Tuning
TL;DR: A wide-range clock generation phase-locked loop incorporating several features that make it suitable for integration in highly scaled processes is described, including a fully differential supply regulated tuning scheme and the charge pump uses a resistor rather than an active current source to define the pumping current.
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