Journal ArticleDOI
A Novel Truncated V-Groove 4H-SiC MOSFET with High Avalanche Breakdown Voltage and Low Specific on-Resistance
Takeyoshi Masuda,Keiji Wada,Toru Hiyoshi,Yu Saitoh,Hideto Tamaso,Mitsuhiko Sakai,Kenji Hiratsuka,Yasuki Mikamura,Masanori Nishiguchi,Tomoaki Hatayama,Hiroshi Yano +10 more
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TLDR
In this paper, a novel trench SiC-MOSFET with buried p+ regions and demonstrated the high breakdown voltage of 1700 V and specific on-resistance of 35 mΩcm2.Abstract:
A breakdown of a conventional trench SiC-MOSFET is caused by oxide breakdown at the bottom of the trench We have fabricated a novel trench SiC-MOSFET with buried p+ regions and demonstrated the high breakdown voltage of 1700 V and the specific on-resistance of 35 mΩcm2read more
Citations
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Journal ArticleDOI
Novel Designed SiC Devices for High Power and High Efficiency Systems
Yasuki Mikamura,Kenji Hiratsuka,Takashi Tsuno,Hisato Michikoshi,So Tanaka,Takeyoshi Masuda,Keiji Wada,Taku Horii,Jun Genba,Toru Hiyoshi,Takeshi Sekiguchi +10 more
TL;DR: In this article, two types of 4H-silicon carbide (SiC) MOSFETs are proposed, one is a V-groove trench and the other is a double implanted MOS-FET with the carefully designed junction termination extension and field-limiting rings.
Journal ArticleDOI
0.97 mΩcm 2 /820 V 4H-SiC super junction V-groove trench MOSFET
T. Masuda,R. Kosugi,Toru Hiyoshi +2 more
TL;DR: In this article, a Super Junction (SJ) V-groove trench MOSFET was fabricated and demonstrated a low specific on-resistance (R on A) of 0.97 mΩcm2 and a blocking voltage (V b ) of 820 V.
Journal ArticleDOI
Practical applications of SiC-MOSFETs and further developments
TL;DR: In this article, the trade-off between the threshold voltage and channel mobility was reduced by a new gate oxide process and the optimization of the dopant concentration in the drift layer and a reduction of wafer thickness.
Proceedings ArticleDOI
The optimised design and characterization of 1200 V / 2.0 mΩ cm 2 4H-SiC V-groove trench MOSFETs
Kosuke Uchida,Yu Saitoh,Toru Hiyoshi,Takeyoshi Masuda,Keiji Wada,Hideto Tamaso,Tomoaki Hatayama,Kenji Hiratsuka,Takashi Tsuno,Masaki Furumai,Yasuki Mikamura +10 more
TL;DR: In this article, a V-groove trench MOSFET with a 4H-SiC{0-33-8} face as the trench sidewall for the channel region and a buried p+ region in the epitaxial layer has been investigated.
Journal ArticleDOI
Micro-structural analysis of local damage introduced in subsurface regions of 4H-SiC wafers during chemo-mechanical polishing
Hideki Sako,Hirofumi Matsuhata,Masayuki Sasaki,Masatake Nagaya,Takanori Kido,Kenji Kawata,Tomohisa Kato,Junji Senzaki,Makoto Kitabatake,Hajime Okumura +9 more
TL;DR: In this article, the surface morphology and lattice defect structures in the subsurface regions of 4H-SiC wafers introduced during chemo-mechanical polishing (CMP) were studied by scanning electron microscopy.
References
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Journal ArticleDOI
Interface properties in metal-oxide-semiconductor structures on n-type 4H-SiC(033̄8)
TL;DR: In this paper, the interface properties of SiO2/4H-SiC(0338) were characterized using n-type metaloxide-semiconductor structures fabricated by wet oxidation.
Journal ArticleDOI
Improvement of Interface State and Channel Mobility Using 4H-SiC (0-33-8) Face
TL;DR: In this paper, the authors characterized MOS devices fabricated on 4H-SiC (0-33-8) face and showed that the field effect channel mobility obtained from lateral MOSFET was 80 cm2/Vs, in spite of a high p-well concentration of 5x1017 cm-3.
Journal ArticleDOI
4H-SiC Trench MOSFET with Thick Bottom Oxide
Hidefumi Takaya,Jun Morimoto,Toshimasa Yamamoto,Jun Sakakibara,Yukihiko Watanabe,Narumasa Soejima,Kimimori Hamada +6 more
TL;DR: In this paper, a 4H-SiC trench MOSFET was developed that features trench gates with a thick oxide layer on the bottoms of the trenches, and the maximum electric field strength and gate-drain charge of this device are 46% and 38%, respectively lower than that of a conventional MOSFLET.