3D IC optimal layout design
A parallel and distributed topological approach
Katarzyna Grzesiak-Kopeć
a
* and Maciej Ogorzałek
b
a,b
Department of Information Technologies, Jagiellonian University in Kraków, Poland
*katarzyna.grzesiak-kopec@uj.edu.pl
The task of 3D ICs layout design involves the assembly of millions of
components taking into account many different requirements and constraints such
as topological, wiring or manufacturability ones. It is a NP-hard problem that
requires new non-deterministic and heuristic algorithms. Considering the time
complexity, the commonly applied Fiduccia-Mattheyses partitioning algorithm is
superior to any other local search method. Nevertheless, it can often miss to reach
a quasi-optimal solution in 3D spaces. The presented approach uses an original
3D layout graph partitioning heuristics implemented with use of the extremal
optimization method. The goal is to minimize the total wire-length in the chip. In
order to improve the time complexity a parallel and distributed Java
implementation is applied. Inside one Java Virtual Machine separate optimization
algorithms are executed by independent threads. The work may also be shared
among different machines by means of The Java Remote Method Invocation
system.
Keywords: 3D floorplanning; layout optimization; physical design; partitioning;
Introduction
Optimal layout design is one of the main engineering design tasks. Optimal is a key
word for a design that optimizes a set of goals and satisfies a set of constraints in the
same time. Both goals and constraints are often conflicting requirements like
miniaturization and usability, low production cost and high quality or practical and
aesthetic reasons. Layout design may be found in the literature under different headings,
e. g. packing, packaging, spatial arrangement, floor-layout, configuration or component
layout. Thus, the search space of optimal layout design solutions is composed of: (1)
design components and their topological connections and (2) design objectives and
constraints. Usually, this space is too large to perform an effective deterministic search
procedure and some heuristic algorithms are applied to obtain a globally near-optimal
solution. Moreover, the ongoing technological development causes the enormous
increase of systems complexity and the number of components to consider. The
electronic industry is the best example of this progress. In the year 2017, the transistor
count (a number of transistors on an integrated circuit (IC)) exceeded 19 billions!
(Mujtaba 2017). Hence, the physical arrangement of chip components comprises a
myriad of conditions.
Even though the concept of 3-dimensional (3D) circuits integration was first
demonstrated as early as in 1979 (Geis et al. 1979) and attracted researchers from
industries as well as academics, the 2-dimensional (2D) technology was scaling so well,
that there was no market pull to develop it. Nowadays 3D ICs design is being
reconsidered and become a sine qua non for the silicon world. It definitely improves
circuit blocks packing density and dramatically decreases the total interconnect wire
length. Along with the interconnect wire length reduction the power consumption is
decreased as well. The third dimension allows heterogeneous technology integration
such as digital and analog. Different components can be manufactured separately
according to their technology and then stack together on a single chip. And last but not
least, 3D design not only gives a smaller footprint but the total volume minimization,
which is very suitable for commonly used mobile devices (Dong and Xie 2009). There
are two major groups of 3D integration technologies: integration using chip stacking
and Through Silicon Vias (TSVs), and native 3D integration. The latter approach is still
in its infancy. Despite the abundance of electronic design automation tools for 2D
integration, there is still a great need for the specific 3D tools, methods and flows to
support the growth of the 3D IC market. Most available software packages are
extensions of those used for planar (2D) design (De Micheli et al. 2011).
The proposed native 3D layout design approach introduces three separate design
representation layers, namely the semantic layer, the presentation layer and the
optimization control one (Grzesiak-Kopeć and Ogorzałek 2014). Possible solutions are
generated with use of a simple shape grammar supervised by an intelligent derivation
controller. The shape grammar is defined by the designer, who also provides a specific
design knowledge in a form of predicates. The predicates are fed into the generation and
optimization procedures. The total wire-length of a generated result may be further
optimized adopting a knowledge intensive 3D ICs layout hypergraph representation
described in (Grzesiak-Kopeć and Ogorzałek 2015a), together with the elaborated
neighbourhood optimization heuristics presented in (Grzesiak-Kopeć and Ogorzałek
2015b).
This article mainly deals with the total wire-length minimization. The main
novel contribution is the volume optimization procedure for eliminating gaps/empty
spaces in the generated 3D structure. The 3-step intelligent wire-length optimization
approach is illustrated by the example of application to the MCNC benchmark circuits
(MCNC) using a parallel and distributed Java implementation. First, the knowledge
intensive 3D ICs layout hypergraph representation together with the elaborated
neighbourhood optimization heuristics are introduced. Then, the wire-length extremal
optimization is described. After that, the procedure of the volume optimization together
with the parallel and distributed implementation are explained. Finally, the proposed
wire-length optimization heuristics is applied to the MCNC set of benchmark circuits
and the experimental results are reported.
Related work
The physical arrangement of components plays a crucial role in integrated
circuit design. It directly affects circuit performance, area, reliability, power, and
manufacturing yield (Kahng et al. 2011). It enables assessment of system architecture
decisions and estimation of delay and congestion caused by wiring (Wang et al. 2009).
The today’s 3D ICs technology still has various limitations such as a layer-like
structure, where a number of device layers is restricted and the inter-layer height is
fixed. Still, a quasi-3D placement problem is much more complex than a true-2D one.
Generally, the placement problem is known to be NP-hard (Garey and Johnson 1979,
Lengauer 1990). Adding an extra dimension to the solution space definitely increases
the difficulty of the circuit design task in many aspects. When taking into account a
placement problem with n components and k layers, a 2D solution may be divided into
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different k-layer 3D floorplans (Li et al. 2006). Thus the solution space
complexity raises by this number times and results in longer searching time and/or
worse placement quality. Common techniques for global placements are: partitioning-
based algorithms, analytic techniques and stochastic algorithms (Kahng et al. 2011,
Hentschke 2007).
Recursive partitioning are constructive techniques with average CPU
requirements and versatility. The netlist and the layout are recursively divided into
smaller sets/problems according to a cut-based cost function until the parts are small
enough to be solved optimally (Taghavi 2005). Common algorithms used to minimize
the number of cut nets are the Kernighan-Lin (Kernighan and Lin 1970) and the
Fiduccia-Mattheyses algorithm (Fiduccia and Mattheyses 1982). The most popular is
the latter which is both computationally effective (a linear time heuristics) and easily
adjustable to different fitness functions. It consists of three stages: coarsening, initial
partitioning and uncoarsening. During the coarsening phase, the netlist is successively
contracted until it is small enough to be plausibly partitioned in the initial partitioning
phase. The selected strategy strongly determines general quality of the partition. The
contraction is reversed at the time of the uncoarsening phase. The achieved initial
partition is mapped to the more comprehensive netlist graph and the solution is
improved by a local search algorithm.
Analytic techniques, such as quadratic placement and force-directed placement,
are constructive ones with relatively low CPU requirements and average versatility
(Eisenmann and Johannes 1998, Obermeier and Johannes 2004). They use an objective
quadratic or otherwise non-convex function, that can be minimized/maximized via
mathematical analysis. Quadratic placement is a two-stage approach. The first stage is a
global placement that minimizes the quadratic function with respect to the component
centers. The obtained overlapping (illegal) solution is corrected during detailed
placement to give a final placement result. A special case of quadratic placement is the
force-directed placement where the mechanical mass-spring system analogy is used to
represent components and wires. The attraction force between components is directly
proportional to their distance. The goal is to reach a placement in a state of force
equilibrium.
Stochastic algorithms introduce a random factor into the cost function
optimization procedure. The best known stochastic placement algorithm is simulated
annealing (SA). SA is an iterative approach with high CPU requirements where not
much memory but a long execution time is needed to reach the desired solution (Sechen
1988, Wong et al. 1988, Taghavi et al. 2005, Chen and Chang 2006). A generated initial
placement is perturbed until the annealing process reaches an equilibrium state or the
algorithm stops after a prescribed number of iterations.
