Proceedings ArticleDOI
Address generation for nanowire decoders
Jia Wang,Ming-Yang Kao,Hai Zhou +2 more
- pp 525-528
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TLDR
A mathematical model of the nanowire decoders for the generation of the proper addresses is developed and it is proved that the maximum number of the properly addresses can be generated in finite time.Abstract:
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with CMOS circuits, nanowire decoders were invented. Due to the stochastic nature of the nanoscale fabrication, the decoder addresses that address the nanowires selectively must be generated after fabrication. In this paper, we develop a mathematical model of the nanowire decoders for the generation of the proper addresses. Assuming a simple testing approach calledon-off measurement, we prove that the maximum number of the proper addresses can be generated in finite time. We design the algorithms to generate the required number of the proper addresses. Experimental results confirm the efficiency of our algorithms.read more
Citations
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Proceedings ArticleDOI
Nanowire addressing with randomized-contact decoders
Eric Rachlin,John E. Savage +1 more
TL;DR: The number of MWs required to produce a correctly functioning RCD with high probability is tightly bound, and it is shown that the number ofMWs is logarithmic in thenumber of NWs, even when errors occur.
Journal ArticleDOI
Nanowire addressing with randomized-contact decoders
Eric Rachlin,John E. Savage +1 more
TL;DR: An unexpected tradeoff between testing time and the number of MWs required by an RCD is demonstrated, which requires more area than the MWs themselves, but has received little attention elsewhere.
System-level optimizations for high performance dsm circuits
TL;DR: This dissertation presents an optimal minimum area retiming algorithm that incrementally relocates flip-flops in a sequential circuit without changing its functionality subject to a clock period bound and investigates sequential system optimization techniques for system optimizations under performance bounds.
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Defect tolerance at the end of the roadmap
M. Mishra,Seth Copen Goldstein +1 more
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