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Analysis and Optimal Design of High Frequency and High Efficiency Asymmetrical
Half-Bridge Flyback Converters
Li, Mingxiao; Ouyang, Ziwei; Andersen, Michael A. E.
Published in:
IEEE Transactions on Industrial Electronics
Link to article, DOI:
10.1109/tie.2019.2950845
Publication date:
2020
Document Version
Peer reviewed version
Link back to DTU Orbit
Citation (APA):
Li, M., Ouyang, Z., & Andersen, M. A. E. (2020). Analysis and Optimal Design of High Frequency and High
Efficiency Asymmetrical Half-Bridge Flyback Converters. IEEE Transactions on Industrial Electronics, 67(10),
8312 - 8321. https://doi.org/10.1109/tie.2019.2950845
1
Abstract—The asymmetrical half-bridge (AHB)
flyback converter is capable to achieve zero voltage
switching (ZVS) and has lower voltage stress compared
to the active clamp flyback converter (ACF). This
topology gives much margin for components selection
and transformer turns ratio design. It is well adapted to
voltage step-down applications. However, the optimal
design for AHB flyback converter taking current dip
effect causing by components parasitic capacitances,
and each component effect to power loss into
consideration has never been explored. This paper gives
detailed operation and mathematical analyses of this
effect. The optimal design procedure with the
consideration of each circuit parameter is presented in
this paper. The transformer benefits low power loss from
interleaving winding layout. A 56W/inch
3
1MHz 65W
prototype with 100V-250V input is built to verify the
feasibility of the converter. Experimental results show
the peak efficiency 96.5% is achieved with 127V input
and the whole system efficiency under the entire input
voltage range is above 93%.
Index Term— AHB flyback converter, high efficiency,
voltage step down applications
I. INTRODUCTION
ith the increasing demand for size reduction and high
power density, high frequency operation provides a way
to achieve these goals. The emerging gallium nitride (GaN)
devices open the door for Megahertz (MHz) range switching
frequency operation. GaN devices show better performance
than silicon MOSFETs under a similar voltage and current
ratings, such as smaller output capacitance, lower gate
charge and smaller package. Thus GaN devices can be
applied to a considerably high frequency converters design
[1]-[6].
Among many DC/DC converters, flyback converters have
been widely used in many applications, such as switching
mode power supplies, adaptors for tablets and smartphones,
PV systems, etc. However, traditional flyback converter
operating at hard switching mode cannot reach high
efficiency at high frequency. Both voltage and current stress
are very high due to the energy stored in transformer leakage
inductance. The conventional passive clamping method
helps reduce the leakage energy by using the clamp resistor.
This reduces the switch voltage stress, but the efficiency is
not improved. Active clamp flyback converters have been
proposed in [6]-[8] to fully utilize the leakage energy to
achieve soft-switching. It has been proved to achieve high
efficiency at high frequency. Many publications have done
excellent works on ACF design [9]-[17]. However, the high
voltage stress for ACF is still a problem. It poses obstacles
to components selection and transformer design.
The AHB flyback converter has lower voltage stress
compared to ACF and is also capable to achieve soft-
switching, which is gaining popularity. It can achieve strong
output voltage regulation through PWM control, which is
the same with ACF. On the other hand, LLC is not suitable
to be used in the applications with a wide input voltage
range, whose regulation capability relies on the small
inductance ratio of magnetizing inductance to resonant
inductance. A large resonant inductor is required, leading to
small power density and low efficiency. This topology is not
considered in this paper.
Many publications have done excellent analyses on AHB
flyback converter. It can be regarded as a buck converter
with a transformer [18]-[23]. Thus it is well adapted to
voltage step-down applications. The switching loss is
reduced and a larger margin for components selection and
turns ratio design are given. Detailed operating principles
can be found in [18][20][22]. The hybrid-switching
technique is proposed in [23] to achieve ZVS for primary
switches and ZCS for the secondary rectifier. However, ZCS
realization relies on the resonance between the resonant
inductor and resonant capacitor. It leads to high primary and
secondary RMS current. Detailed analysis can be found in
this paper. Literature [24] gives conventional analysis and
design procedure for AHB flyback converter, but the current
dip effect is not considered. It affects primary and secondary
RMS current.
To obtain soft-switching properties, capacitances of
switches are always taken into consideration, as many
publications have explored [19][20][24][25]. However, the
current dip effect due to the current shared by the primary
and secondary capacitances has never been mentioned or
investigated in optimal design procedure for AHB flyback
converters. At Mega Hz operation, they are of great
importance to design a high performance converter. This
paper gives detailed analyses of the current dip effect due to
the current shared by the primary and secondary
capacitances, which affects both primary and secondary
RMS current and further power loss. This effect can be used
to select primary and secondary switches. The flux
cancellation in the transformer is first mentioned in this
paper. The AHB flyback converter benefits low winding loss
from interleaving winding layout. Additionally, the impact
of the resonant capacitor on primary and secondary RMS
current and the optimal magnetizing inductance design with
the consideration of power loss are investigated. An optimal
design procedure is given and iterations are then conducted
to select the turn ratio with minimum power loss. The half-
turn winding paralleled concept proposed in [26] is adopted
to minimize the transformer AC resistance.
Analysis and Optimal Design of High Frequency
and High Efficiency Asymmetrical Half-Bridge
Flyback Converters
Mingxiao Li, Student Member, IEEE, Ziwei Ouyang, Senior Member, IEEE
and Michael A.E. Andersen, Member, IEEE
W
Manuscript received April 10, 2019; revised August 13, 2019 and
September 16, 2019; accepted October, 2019. (Corresponding
author: Ziwei Ouyang)
The authors are with the Department of Electrical Engineering,
Technical University of Denmark, Kgs. Lyngby 2800, Denmark (e-
mail: mingxli@elektro.dtu.dk; zo@elektro.dtu.dk;ma@elektro.dtu.dk).
2
This paper is organized as follows: Section II gives the
detailed operating principle and analyses of the current dip
effect along with mathematical equations and waveforms. A
comparison of the traditional ACF and the AHB flyback
converter is also illustrated. The optimal design procedure is
described in Section III. A 56W/inch
3
1MHz 65W with peak
efficiency 96.5% prototype is demonstrated in Section IV.
Section V concludes this paper.
Vcr
n:1
Q1
Lr
Lm
C
oss
Q2
C
oss
i
Lr
V
in
Vo
V
SR
i
Lm
C
sj
Transformer
i
ds1
i
s
V
ds1
V
ds2
SR
(a)
Vcr
n:1
Q1
Lr
Lm
C
oss
Q2
C
oss
i
Lr
V
in
Vo
i
Lm
Transformer
C
sj
SR
i
s
V
SR
(b)
Fig.1 On the top/bottom of the schematics
t
1
t
2
t
3
t
4
t
5
V
gs2
V
gs1
i
Lr
/i
Lm
V
ds2
V
ds1
V
d
V
in
V
in
/n
V
in
i
s
t
d
Fig.2 Waveforms of the proposed topology
II. ANALYSES OF THE AHB FLYBACK CONVERTER
Two configurations of the AHB flyback converter are
illustrated in Fig.1 (a) and Fig.1 (b), respectively. Q
1
and Q
2
form a half-bridge configuration. The switch node is
connected to the transformer and the resonant capacitor. The
switch Q
1
toggles complementarily concerning Q
2
. Thus the
voltage stress on Q
1
and Q
2
is always clamped by the input
voltage, regardless of the transformer turns ratio and output
voltage. Waveforms of the proposed converter operating
close to the CCM/DCM mode boundary is shown in Fig.2.
Since the operating principles of these two configurations
are identical, only the Fig.1(a) is analyzed. Both steady-state
and operating principles analyses of this topology are
discussed in this section.
A. Steady-state analyses
To analyze this circuit, the following assumptions are
made
—The output voltage V
o
is a constant value
—The resonant inductance L
r
is much smaller than the
magnetizing inductance L
m
.
—Conduction power losses of all switches are neglected.
—The resonant capacitor C
r
can be taken as a constant
voltage source.
—The conduction times for Q
1
and Q
2
are (1-D)T
s
and
DTs, respectively, where D is the duty cycle for Q
2
and T
s
is
the switching period. Dead time is neglect in the steady-state
analysis.
Based on the assumptions mentioned above, the voltage
transfer ratio V
o
/V
in
and the voltage across the resonant
capacitor V
cr
can be obtained when voltage second balance
is applied to magnetizing inductance L
m
. When the bottom
switch Q
2
turns on, the voltage across the transformer
primary winding is V
in
-V
cr
and Q
1
is clamped by the input
voltage V
in
. In the next time interval, Q
2
turns off while Q
1
turns on. The voltage applied to the transformer primary
winding becomes –V
cr
. Q
2
is clamped by the input voltage
V
in
. Apply voltage second balance on magnetizing
inductance and the voltage across the resonant capacitor can
be expressed by (1)
1
in Cr Cr
DVVVD
Cr in
VVD (1)
The converter is operating close to the CCM/DCM
boundary with the relatively small magnetizing current. It
has a negligible effect on (1). The voltage-second-balance
law can still be used. The same approximation can be found
in [14][24][25].
nV
o
is applied to magnetizing inductance during the
period when Q
1
is on. If L
r
cannot be ignored, V
cr
should be
expressed by
1
r
Cr o
m
L
VnV
L
Based on the given assumption, L
r
is much smaller than
the magnetizing inductance L
m
. Thus V
Cr
is very close to the
reflected output voltage nV
o
. The same approximation can
be found in [14][24][25]. The voltage transfer ratio can be
found in (2)
1
in Cr o
DVnVDV
o
in
V
D
Vn
(2)
T
hen the voltage across secondary synchronous rectifier
(SR) when Q
2
turns on, V
SR
can be found to be
/
SR in
VVn (3)
TABLE I
C
OMPARISON BETWEEN TRADITIONAL ACF AND AHB FLYBACK
V
ds1
/V
ds2
V
SR
V
o
/V
in
ACF V
in
+nV
o
V
in
/n+V
o
D/n(1-D)
AHB flyback V
in
V
in
/n D/n
3
The comparison between ACF and AHB flyback
converter is shown in TABLE I. The voltage stresses for
both primary and secondary switches are reduced, which
offers much margin to select primary and secondary
components and transformer turns ratio. It is also
worthwhile to point out that the voltage stress for the
primary main switch of ACF is higher than V
in
+nV
o
due to
the voltage across the leakage inductance. On the other hand,
that for the AHB flyback converter is always clamped by the
input voltage V
in
. This provides a safe selection for primary
switches. More importantly, since there is no 1-D in the
denominator of the voltage transfer ratio for the AHB
flyback converter, it is more preferable to be used in voltage
step down cases. In another word, the traditional ACF
converter can be regarded as a buck-boost converter, while
the AHB flyback converter functions as a buck converter.
Its capability to step the voltage down is higher than the
traditional ACF. With all mentioned merits, it is more
preferable for voltage step down applications.
B. Operating principles analyses
Stage 1 (t
1
<t<t
2
): Q
2
ZVS turns on at t
1
and then the drain-
to-source voltage of Q
1
V
ds1
is clamped by input voltage V
in.
The secondary rectifier is blocked. The energy is stored in
the transformer. The magnetizing current i
m
increases
linearly together with the resonant current i
Lr
and can be
expressed by
1
in Cr
Lr Lm Lr
rm
VV
ititit t
LL
(4)
This time interval ends when Q
2
turns off at t
2
.
Stage 2 (t
2
<t<t
3
): A current dip happens to the resonant
current i
Lr
during the transient period after Q
2
turns off at
time t
2
, which can be observed from Fig.2. It affects both
primary and secondary RMS current. Detailed analysis of
this effect will be given in the following description.
V
in
L
m
L
r
C
oss
C
ps
nV
o
C
oss
V
Cr
i
Lm
i
Lr
Fig.3 Equivalent resonance circuit
Resonance occurs among L
r
, output capacitances C
oss
of
primary switches and secondary rectifier output capacitance
C
sj
. The equivalent circuit is shown in Fig.3. C
ps
is C
sj
referred to the primary side. Assume the magnetizing current
i
m
maintains the peak value I
Lm_max
during this transient
period, which can be calculated by
__
1
2
o
m
Lm max Lm avg
s
d
nV D
L
I
T
I
t
(5)
___
o
Lm avg Lr avg s avg
I
II
n
I
(6)
where t
d
is the dead time as shown in Fig.2. Only the dead
time between
t
4
to t
5
is considered because it takes longer
time than that from
t
2
to t
3
for the small reverse magnetizing
current to charge and discharge the parasitic capacitances;
I
o
is the output current.
The average resonant current I
Lr_avg
is
zero when the law of charge balance is applied to the
resonant capacitor.
Then the resonant current
i
Lr
can be solved by [14]
__
2
cos
2C C 2
ps
oss
L
rLmmax Lmmax r
oss ps oss ps
C
C
it I I t
CC
(7)
where
2
1/
2
oss ps
rr
oss ps
CC
L
CC
(8)
Due to the large peak magnetizing current I
Lm_max
, Q
1
is
usually fully discharged within one resonance period. The
maximum current dip when the resonance is longer than half
period can be obtained by
__
2
2
ps
dip max Lm max
oss ps
C
I
CC
I
(9)
Equation (9) illustrates that the resonant current dip is due
to the current shared by the primary and secondary
capacitances. The maximum current dip is determined by the
ratio
C
ps
/C
oss
.
If the resonance is shorter than the half period, the current
dip is lower. Actually, the resonance stops when
C
oss
of Q
1
is fully discharged or
C
sj
of the secondary rectifier is fully
discharged. The expressions for
V
ds1
and V
SR
are given as
follows:
__
1
sin
.
22 2
Lm max Lm max ps
r
ds in
oss ps oss ps r oss
ItIC
t
V
CC CC C
V
t
(10)
__
sin
.
22
Lm max Lm max ps
r
SR in
oss ps oss ps r ps
ItIC
t
V
CC C
n
CC
V t
(11)
0
50
100
150
V
ds1
(V)
nV
SR
(V)
Tr/2
Tr
(a)
0
50
100
150
V
ds1
(V)
nV
SR
(V)
Tr/2 Tr
(b)
Fig.4 V
ds1
and V
SR
waveforms during ZVS transition period when (a)
C
oss
=8pF and C
sj
=200pF; (b)C
oss
=17pF and C
sj
=400pF
L
m
L
r
V
cr
nV
o
i
Lr
i
Lm
Fig.5 Equivalent circuit of L
r
and C
r
resonant process
4
Large
C
oss
and C
ps
give longer resonance, which is longer
than half resonance period. In this case,
V
SR
drops to zero
first. By contrast, small
C
oss
and C
ps
give short resonance,
which is shorter than half resonance period and
V
ds1
will
drops to zero first. This phenomenon is shown in Fig.4. If
the resonance is much smaller than the half resonance period
T
r
, sin(ω
r
t) can be replaced by ω
r
t. V
ds1
decreases to zero
linearly. Thus it will not join in the resonance and the
resonance current expressions can be solved by
_1
1
s i n
in Cr
mCr
m
Lr Lm max r
r
VV
LV
LLr
it I t
Z
(12)
1
/, 1/
rpsrpsrr
Z
LC LC
(13)
The maximum current dip becomes
_
1
1
1/
r
in Cr
m
dip max
rmr
L
VV
L
I
LLZ
(14)
Equation (14) shows when the resonance is less than half
resonance period, the ratio of
L
r
/C
ps
will affect the maximum
current dip. Since the magnetizing inductance
L
m
is much
larger than
L
r
, I
dip_max
depends on Z
r1
.
Stage 3 (
t
3
<t<t
4
): After the current dip happens to i
Lr
, Q
1
and secondary rectifier start to conduct current. Resonance
occurs between
L
r
and C
r
. The difference between i
Lr
and i
Lm
is transferred to the secondary side. The magnetizing
inductance is clamped by
nV
o
. The resonant process of L
r
and
C
r
is the same with traditional active clamp flyback
converter, but the initial conditions are different. The
equivalent resonant circuit is shown in Fig.5 and the
expressions for magnetizing current
i
Lm
and resonant current
i
Lr
during this time interval are shown as follows
_Lm Lm max
m
nVo
iI t
L
t
(15)
_
_
cos sin
oCrini
Lr Lr ini
nV V
it I t t
Z
(16)
__
_
()
2
L
mmax Lmmin s
Cr ini o
r
IIDT
VnV
C
(17)
__
1
2
()
os
Lm min Lm avg
m
d
nV D T
II
L
t
(18)
1/ ,
r
rr
r
L
LC Z
C
(19)
where V
Cr_ini
is the initial voltage across the resonant
capacitor before the resonance starts and can be estimated
based on the charge balance;
I
Lm_min
is the minimum
magnetizing current;
I
Lr_ini
is the resonant current after the
current dip. It can be expressed by
__max
2
2
m
oss ps
Lr ini L
oss ps
CC
II
CC
(20)
or
_
1
_
in Cr
mCr
m
Lm max
r
Lr ini
VV
LV
LLr
I
Z
I
(21)
depending on the resonance longer or shorter than the half
resonance period.
Stage 4 (
t
4
<t<t
5
): The current dip also occurs during this
ZVS transition period after
Q
1
turns off. The equivalent
resonant circuit is also the same with the previous ZVS
transition period as shown in Fig.3, while the initial
conditions are different. The similar expression for resonant
current
i
Lr
is shown as follows:
44
2
cos
2C C 2
Lr Lr
C
C
ps
oss
it t
r
Lr
CC
oss ps oss ps
it it
(22)
Like in the previous ZVS transition period, the current dip
occurs to the resonant current
i
Lr
. This is due to the current
divider effect due to the output capacitance of primary and
secondary switches. The resonant current
i
Lr
ringing
amplitude is affected by the ratio
C
ps
/C
oss
. High
C
ps
/C
oss
may
lead
i
Lr
to be positive, which affects the V
ds2
decreasing rate.
If
C
ps
is too large, it requires longer dead time for the
resonant current
i
Lr
to discharge. This will affect the ZVS
transition period at high frequency. The expression for
V
ds2
is
__
2
1
sin
22 2
Lm min Lm min ps
ds in r
oss ps oss ps r oss
ItIC
Vt
CC C
Vt
CC
(23)
A simulation is conducted to illustrate this phenomenon.
As shown in Fig.6, the blue curve with low
C
ps
is decreasing
faster and turns off earlier than the red curve with high
C
ps
.
In high frequency converter design, dead time control is of
great importance. It is desirable to have a very short ZVS
transition period to minimize the circulation power loss.
20 40 60 80 100 120
t(ns)
0
20
40
60
80
100
120
V
ds
(V)
C
ps
/C
oss
=2.86
C
ps
/C
oss
=1
Fig.6 Drain-to-source voltage for Q
2
during ZVS transition time
Additionally, due to the small I
Lm_min
, it takes several
resonant periods to fully discharge
Q
2
. This can also be
observed in Fig.6. On the other hand, the magnetizing
current
I
Lm_max
is much larger than I
Lm_min
. During the ZVS
transition after
Q
2
turns off, Q
1
is usually fully discharged
within one resonant period. The decreasing rate of
V
ds1
is
almost linear. Therefore, only the dead time from
t
4
to t
5
is
considered.
This period ends when
Q
2
is fully discharged and realizes
ZVS turn on.
Q
1
will be clamped by the input voltage.
TABLE II
S
PECIFICATION
Quantity Range
V
in
(V) 100~250
V
o
(V) 19.3
P
o
(W) 65
f
s
1MHz
III. OPTIMAL DESIGN PROCEDURE
The specification is shown in TABLE II. Since the
voltage stress for primary devices is reduced to input voltage
V
in
for the proposed topology, both switches and turns ratio
selection have a larger margin than traditional ACF. In this
design, the converter is designed to operate at discontinues
conduction mode (DCM). The negative
i
Lm
helps ZVS
