Book ChapterDOI
Architecture Template and Design Flow to Support Application Parallelism on Reconfigurable Platforms
Sergei Sawitzki,Rainer G. Spallek +1 more
- pp 1119-1122
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TLDR
To derive architecture instances from the template, a design environment called DEfInE is used, which integrates some existing academic and industrial tools with ReSArT-specific components, developed as a part of this work.Abstract:
This paper introduces the ReSArT ( Reconfigurable Scalable Architecture Template). Based on a suitable design space model, ReSArT is parametrizable, scalable, and able to support all levels of parallelism. To derive architecture instances from the template, a design environment called DEfInE ( Design Environment for ReSArT Instance G eneration) is used, which integrates some existing academic and industrial tools with ReSArT-specific components, developed as a part of this work. Different architecture instances were tested with a set of 10 benchmark applications as a proof of concept, achieving a maximum degree of parallelism of 30 and an average degree of parallelism of nearly 20 16-bit operations per cycle.read more
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Journal Article
Inter-processor connection reconfiguration based on dynamic look-ahead control of multiple crossbar switches
TL;DR: Automatic program structuring is proposed based on the analysis of parallel program graphs that finds the partition into sections that minimizes the execution time of a program executed with the look-ahead created connections.
Book ChapterDOI
Inter-processor Connection Reconfiguration Based on Dynamic Look-Ahead Control of Multiple Crossbar Switches
TL;DR: In this paper, a look-ahead dynamic reconfiguration of inter-processor connections is proposed to reduce the execution time of a program executed with the look-forward created connections.
References
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SIS : A System for Sequential Circuit Synthesis
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Architecture and CAD for Deep-Submicron FPGAS
TL;DR: From the Publisher: Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPG as implemented in deep-submicron processes.
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Building and using a highly parallel programmable logic array
TL;DR: A two-slot addition called Splash, which enables a Sun workstation to outperform a Cray-2 on certain applications, is discussed and an example application, that of sequence comparison, is given.
Journal ArticleDOI
A novel paradigm of parallel computation and its use to implement simple high-performance hardware
TL;DR: A novel (non-von Neumann) paradigm of parallel computation supporting a much more efficient implementation of parallel algorithms is introduced and its flexibility is illustrated by simple DSP and image processing examples.
Book ChapterDOI
A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware
TL;DR: A novel (non-von Neumann) paradigm of parallel computation supporting a much more efficient implementation of parallel algorithms than known from von Neumann computers is introduced.
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