Journal ArticleDOI
Auto-Zeroing Static Phase Offset in DLLs Using a Digitally Programmable Sensing Circuit
TLDR
This brief presents a static phase offset (SPO) reduction technique through auto-zeroing in a delay-locked loop (DLL) and proposes a self-calibrated, digitally programmable, sensing circuit that can measure both the polarity and the magnitude of the SPO.Abstract:
This brief presents a static phase offset (SPO) reduction technique through auto-zeroing in a delay-locked loop (DLL). We propose a self-calibrated, digitally programmable, sensing circuit that can measure both the polarity and the magnitude of the SPO. The SPO is suppressed by tuning a pair of digital-to-time converters (DTCs) at the input of the phase frequency detector (PFD). The proposed technique enables run-time background calibration and can suppress the SPO caused by artifacts from the PFD, charge pump, and loop filter capacitor. Monte Carlo simulation results show that the SPO in a conventional DLL implementation improves from 12.92 ps to 0.90 ps when the proposed auto-zeroing technique is employed.read more
References
More filters
Journal ArticleDOI
Charge pump with perfect current matching characteristics in phase-locked loops
TL;DR: In this paper, the authors proposed a new charge pump circuit with perfect current matching characteristics in a 0.25 /spl mu/m CMOS process with an error amplifier and reference current sources.
Book
Phase-Locking in High-Performance Systems: From Devices to Architectures
TL;DR: Phase-Locking in High-Performance Systems: From Devices to Architectures is a superb reference for anyone working on, or seeking to better understand, this rapidly-developing and increasingly central technology.
Journal ArticleDOI
A DLL-Based Programmable Clock Multiplier in 0.18- $\mu$ m CMOS With ${-}$ 70 dBc Reference Spur
P.C. Maulik,D.A. Mercer +1 more
TL;DR: In this article, a 150-400 MHz programmable clock multiplier using a recirculating DLL is described, which uses a sampling phase detector and employs chopping, auto zeroing and various other circuit techniques to reduce static phase offset and crosstalk between the reference and the output clock.
Journal ArticleDOI
A 250-MHz-2-GHz wide-range delay-locked loop
Byung-Guk Kim,Lee-Sup Kim +1 more
TL;DR: In this paper, a wide-range delay-locked loop (DLL) for a synchronous clocking which supports dynamic frequency scaling and dynamic voltage scaling is described. But the DLL has wide operating range by using multiple phases from its delay line.
Patent
Chopped charge pump
Michael F. Keaveney,William Hunt +1 more
TL;DR: In this paper, a chopped charge pump (80) with matching up and down pulses including a first pair of current sources (84, 86), a second pair (90, 92), and a switching circuit (94) for switching on in a first phase one of each pair to provide up current pulses and the other of each pairs to provide down current pulses.
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