Journal ArticleDOI
Correlation of Radiation Effects in Transistors and Integrated Circuits
F.W. Sexton,James R. Schwank +1 more
TLDR
In this paper, the effects of ionizing radiation on discrete MOS n- and p-channel transistors are correlated with performance degradation of CMOS integrated circuits, and the individual components of radiation induced charge, oxide-trapped charge and interface-state charge, are separated using a subthreshold current technique.Abstract:
The effects of ionizing radiation on discrete MOS n- and p-channel transistors are correlated with performance degradation of CMOS integrated circuits. The individual components of radiation induced charge, oxide-trapped charge and interface-state charge, are separated using a subthreshold current technique. Processing splits and post-irradiation biased anneals are used to vary the ratio of oxide-trapped charge to interface-state charge. It is shown that the effective channel mobility depends to first order on the interface-state charge density. Static power supply current is correlated with the n-channel leakage at zero gate voltage while output drive currents are a function of both threshold voltage and channel mobility. Changes in propagation delay of signals through integrated circuits can be understood when both mobility and threshold voltage are considered as a function of the bias dependent charge buildup. A new transistor switching time figure of merit, t/C, which measures the drain to source drive over a full logic level voltage swing at the drain node, is introduced. This index is then shown to correlate with propagation delay in an IC. Finally, performance changes in an IC are modeled using only the measured buildup of oxide-trapped and interface-state charges from transistors as a function of radiation.read more
Citations
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Journal ArticleDOI
Total Ionizing Dose Effects in MOS and Low-Dose-Rate-Sensitive Linear-Bipolar Devices
TL;DR: An overview of total ionizing dose (TID) effects in MOS and bipolar devices from a historical perspective, focusing primarily on work presented at the annual IEEE Nuclear and Space Radiation Effects Conference (NSREC) is presented in this paper.
Journal ArticleDOI
Challenges in hardening technologies using shallow-trench isolation
TL;DR: In this article, the authors explored the use of device simulations in concert with measurements on test structures to provide detailed physical insight into methods for improving total-dose radiation response and demonstrated the successful conversion of a non-radiation hardened technology with LOCOS isolation (Sandia's CMOS6) into a greater than 1 Mrad(SiO/sub 2/) radiation-hardened shallow-trench isolated technology.
Journal ArticleDOI
Using laboratory X-ray and cobalt-60 irradiations to predict CMOS device response in strategic and space environments
TL;DR: The postirradiation response of CMOS transistors with 30-60-nm gate oxides is investigated as a function of radiation energy, total dose, dose rate, and annealing time and no 'true' dose-rate effects on MOS device response are observed.
Journal ArticleDOI
Border traps: issues for MOS radiation response and long-term reliability
Daniel M. Fleetwood,Marty R. Shaneyfelt,William L. Warren,J.R. Schwank,T.L. Meisenheimer,P.S. Winokur +5 more
TL;DR: In this article, the effects of border traps (near-interfacial oxide traps that can communicate with the underlying Si over a wide range of time scales) on the response of metal-oxide-semiconductor (MOS) devices to ionizing radiation are investigated.
Journal ArticleDOI
Radiation Hardness Assurance Testing of Microelectronic Devices and Integrated Circuits: Radiation Environments, Physical Mechanisms, and Foundations for Hardness Assurance
TL;DR: The purpose of this document is to describe why the test protocols the authors use are constructed the way they are, to answer the question: “Why do they test it that way”?
References
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Journal ArticleDOI
Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces
S.C. Sun,James D. Plummer +1 more
TL;DR: In this paper, an extensive set of experimental results on the behavior of electron surface mobility in thermally oxidized silicon structures are presented, which allow the calculation of electron mobility under a wide variety of substrate, process, and electrical conditions.
Journal ArticleDOI
Correlating the Radiation Response of MOS Capacitors and Transistors
TL;DR: In this paper, a new technique is presented for separating the thresholdvoltage shift of an MOS transistor into shifts due to interface states and trapped-oxide charge, and the radiation responses of MOS capacitors and transistors fabricated on the same wafer are compared.
Journal ArticleDOI
Physical Mechanisms Contributing to Device "Rebound"
Abstract: The physical mechanisms that produce rebound have been identified. The positive increase in threshold voltage during a bias anneal is due to annealing of oxide trapped charge. Rebound can be predicted by measuring the contribution to the threshold voltage from radiation-induced interface states immediately after irradiation.
Journal ArticleDOI
The Effect of Gate Oxide Thickness on the Radiation Hardness of Silicon-Gate CMOS
T. V. Nordstrom,C. F. Gibbon +1 more
TL;DR: In this article, an 8-bit arithmetic logic unit designed with Sandia's Expanded Linear Array (ELA) standard cells was fabricated with gate oxide thickness of 400, 570, and 700 A.
Journal ArticleDOI
Two-Dimensional Modeling of N-Channel MOSFETs including Radiation-Induced Interface and Oxide Charge
C. L. Wilson,J. L. Blue +1 more
TL;DR: In this article, a model of the radiation-induced changes produced in n-channel MOSFETs is presented, which is applicable for the unirradiated device and accurately predicts device characteristics for doses of up to 500 krad(Si).
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Simple technique for separating the effects of interface traps and trapped‐oxide charge in metal‐oxide‐semiconductor transistors
P. J. McWhorter,P. S. Winokur +1 more