Proceedings ArticleDOI
Design and implementation of high speed and high accuracy fixed-width modified booth multiplier for DSP application
Aravind Babu S,Babu Ramki S,K. Sivasankaran +2 more
- pp 1-5
TLDR
An error compensation bias circuit added to a modified encoded booth multiplier to produce a high accuracy fixed-width multiplier that has 37.2% less truncation error as compared to direct truncated fixed width multiplier (DTFM).Abstract:
This paper presents an error compensation bias circuit added to a modified encoded booth multiplier to produce a high accuracy fixed-width multiplier. Fixed-width multiplier is employed in many digital signal processing applications, as most of these systems employ iterative structures with fixed precision. The design has been implemented in TSMC 180nm technology. The design is 14.6% faster than the fixed-width multipliers. The design has 37.2% less truncation error as compared to direct truncated fixed width multiplier (DTFM). The design is embedded with operand isolator technique to ensure low power operation when employed in DSP applications.read more
Citations
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Proceedings ArticleDOI
Implementation of vedic multiplier using Kogge-stone adder
TL;DR: A novel architecture to perform high speed multiplication using ancient vedic mathematics named as Urdhva Triyakbhyam strikes a difference in the actual multiplication process using verilog HDL.
Journal ArticleDOI
Error Compensation Techniques for Fixed-Width Array Multiplier Design — A Technical Survey
TL;DR: This paper provides a comprehensive review of various error compensation techniques for fixed-width multiplier design along with its applications and presents the experimental results of error metrics, including normalized maximum absolute error, normalized mean error and normalized mean-square error to evaluate the accuracy of fixed- width multipliers.
Journal ArticleDOI
High Speed 32-bit Vedic Multiplier for DSP Applications
TL;DR: Two high speed 32-bit Vedic multipliers are designed based on Urdhva-Triyakhbhyam sutra using Verilog HDL and synthesized using cadence tool.
Journal ArticleDOI
An unsigned truncated sequential multiplier with variable error compensation
TL;DR: An n-bit unsigned truncated sequential multiplier with new approaches that compensate for the truncation error is proposed in this paper, and these compensating approaches improve the result accuracy using the (n1)th or nth columns of the partial product matrix dynamically.
References
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High-Speed Arithmetic in Binary Computers
TL;DR: Methods of obtaining high speed in addition, multiplication, and division in parallel binary computers are described and then compared with each other as to efficiency of operation and cost.
Proceedings ArticleDOI
Truncated multiplication with correction constant [for DSP]
TL;DR: The authors present a technique for parallel multiplication which computes the product of two numbers by summing only the most significant columns of the multiplication matrix, along with a correction constant, which minimizes the average and mean square error.
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Area-efficient multipliers for digital signal processing applications
TL;DR: The paper shows that this design strategy can also be applied for the design of two's-complement multipliers and it is shown that the signal-to-noise ratio of the digital filter using a truncated multiplier is better than that using a standard multiplier.
Journal ArticleDOI
Design of low-error fixed-width modified booth multiplier
TL;DR: By simulations, it is shown that quantization error can be reduced up to 50% by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit.
Journal ArticleDOI
Generalized low-error area-efficient fixed-width multipliers
Lan-Da Van,Chih-Chyau Yang +1 more
TL;DR: In this article, a family of low-error area-efficient fixed-width two's-complement multipliers that receive two n-bits numbers and produce an n-bit product is proposed.