Open Access
Design Techniques for Ultra-Low-Voltage and Ultra-Low-Power Pipelined ADCs
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The article was published on 2010-01-01 and is currently open access. It has received 3 citations till now. The article focuses on the topics: Low voltage.read more
Citations
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Proceedings Article
A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC
Eric Siragusa,Ian Galton +1 more
TL;DR: In this article, a 1.8-V 15-bit 40-MSample/s CMOS pipelined analog-to-digital converter with 90-dB spurious-free dynamic range (SFDR) and 72-dB peak SNR over the full Nyquist band is presented.
Dissertation
Pipelined analog-to-digital conversion using current-mode reference shifting
TL;DR: Dissertacao para obtencao do grau de Mestre em Engenharia Electrotecnica e de Computadores
Proceedings Article
A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR
TL;DR: In this article, an ultra-low-voltage CMOS two-stage algorithm ADC with high SFDR and efficient background calibration is presented, which achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping.
References
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Book
Random variables and stochastic processes
TL;DR: An electromagnetic pulse counter having successively operable, contact-operating armatures that are movable to a rest position, an intermediate position and an active position between the main pole and the secondary pole of a magnetic circuit.
Book
CMOS Analog Circuit Design
TL;DR: In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.
Book
Understanding Delta-Sigma Data Converters
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Journal ArticleDOI
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
A.M. Abo,Paul R. Gray +1 more
TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.
Journal ArticleDOI
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
Thomas Byunghak Cho,Paul R. Gray +1 more
TL;DR: This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation.