Open AccessBook
CMOS Analog Circuit Design
TLDR
In this article, the authors present a simple MOS LARGE-SIGNAL MODEL (SPICE Level 1) and a small-signal model for the MOS TRANSISTOR.Abstract:
1.1 ANALOG INTEGRATED CIRCUIT DESIGN 1.2 NOTATION, SYMBOLOGY AND TERMINOLOGY 1.3 ANALOG SIGNAL PROCESSING 1.4 EXAMPLE OF ANALOG VLSI MIXED-SIGNAL CIRCUIT DESIGN 2.1 BASIC MOS SEMICONDUCTOR FABRICATION PROCESSES 2.2 THE PN JUNCTION 2.3 THE MOS TRANSISTOR 2.4 PASSIVE COMPONENTS 2.5 OTHER CONSIDERATIONS OF CMOS TECHNOLOGY 3.1 SIMPLE MOS LARGE-SIGNAL MODEL (SPICE LEVEL 1) 3.2 OTHER MOS LARGE-SIGNAL MODEL PARAMETERS 3.3 SMALL-SIGNAL MODEL FOR THE MOS TRANSISTOR 3.4 COMPUTER SIMULATION MODELS 3.5 SUBTHRESHOLD MOS MODEL 3.6 SPICE SIMULATION OF MOS CIRCUITS 4.1 MOS SWITCH 4.2 MOS DIODE/ACTIVE RESISTOR 4.3 CURRENT SINKS AND SOURCES 4.4 CURRENT MIRRORS 4.5 CURRENT AND VOLTAGE REFERENCES 4.6 BANDGAP REFERENCE 5.1 INVERTERS 5.2 DIFFERENTIAL AMPLIFIERS 5.3 CASCODE AMPLIFIERS 5.4* CURRENT AMPLIFIERS 5.5* OUTPUT AMPLIFIERS/BUFFERS 6.1 DESIGN OF CMOS OP AMPS 6.2 COMPENSATION OF OP AMP 6.3 DESIGN OF TWO-STAGE OP AMPS 6.4 POWER-SUPPLY REJECTION RATIO OF TWO-STAGE OP AMPS 6.5 CASCODE OP AMPS 6.6 SIMULATION AND MEASUREMENT OF OP AMPS 6.7 MACROMODELS FOR OP AMPS 7.1 BUFFERED OP AMPS 7.2 HIGH-SPEED/FREQUENCY OP AMPS 7.3 DIFFERENTIAL-OUTPUT OP AMPS 7.4 MICROPOWER OP AMPS 7.5 LOW NOISE OP AMPS 7.6 LOW VOLTAGE OP AMPS 8.1 CHARACTERIZATION OF A COMPARATOR 8.2 TWO-STAGE, OPEN-LOOP COMPARATOR DESIGN 8.3 OTHER OPEN-LOOP COMPARATORS 8.4 IMPROVING THE PERFORMANCE OF OPEN-LOOP COMPARATORS 8.5 DISCRETE-TIME COMPARATORS 8.6 HIGH-SPEED COMPARATORS APPENDIX A CIRCUIT ANALYSIS FOR ANALOG CIRCUIT DESIGN APPENDIX B INTEGRATED CIRCUIT LAYOUT APPENDIX C CMOS DEVICE CHARACTERIZATION APPENDIX D TIME AND FREQUENCY DOMAIN RELATIONSHIP FOR SECOND-ORDER SYSTEMSread more
Citations
More filters
Journal ArticleDOI
A g/sub m//I/sub D/ based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA
TL;DR: In this paper, a new design methodology based on a unified treatment of all the regions of operation of the MOS transistor is proposed for the design of CMOS analog circuits and especially suited for low power circuits where the moderate inversion region often is used.
Journal ArticleDOI
A high-swing, high-impedance MOS cascode circuit
E. Sackinger,W. Guggenbuhl +1 more
TL;DR: In this paper, a simple cascode with the gate voltage of the cascode transistor being controlled by a feedback amplifier called a regulated cascode is presented, where the minimum output voltage is lower by 30 to 60% while the output conductance and the feedback capacitance are lower by about 100 times.
Journal ArticleDOI
Optimal design of a CMOS op-amp via geometric programming
TL;DR: A new method for determining component values and transistor dimensions for CMOS operational amplifiers (op-amps) is described, showing in detail how the method can be used to size robust designs, i.e., designs guaranteed to meet the specifications for a variety of process conditions and parameters.
Journal ArticleDOI
A high-efficiency CMOS voltage doubler
TL;DR: In this paper, a charge pump cell is used to make a voltage doubler using improved serial switches and a complete power efficiency theory is presented which fits the measurements, and the importance of capacitors is shown with plots of power efficiency versus load and stray capacitors.
Book
Broadband Circuits for Optical Fiber Communication
TL;DR: This paper presents a meta-modelling system that automates the very labor-intensive and therefore time-heavy and therefore expensive and expensive process of manually winding and disconnecting receiver and modulator systems.