Journal ArticleDOI
A 10 b, 20 Msample/s, 35 mW pipeline A/D converter
Thomas Byunghak Cho,Paul R. Gray +1 more
TLDR
This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation.Abstract:Â
This paper describes a 10 b, 20 Msample/s pipeline A/D converter implemented in 1.2 /spl mu/m CMOS technology which achieves a power dissipation of 35 mW at full speed operation. Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline. Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits. Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s. At Nyquist sampling (10 MHz input) SNDR is 55.0 dB. Differential input range is /spl plusmn/1 V, and measured input referred RMS noise is 220 /spl mu/V. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR. >read more
Citations
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Journal ArticleDOI
Analog-to-digital converter survey and analysis
TL;DR: The state-of-the-art of ADCs is surveyed, including experimental converters and commercially available parts, and the distribution of resolution versus sampling rate provides insight into ADC performance limitations.
Journal ArticleDOI
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
A.M. Abo,Paul R. Gray +1 more
TL;DR: In this paper, a 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-digital converter was implemented in a 0.6/spl mu/m CMOS technology.
Journal ArticleDOI
A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Boris Murmann,Bernhard E. Boser +1 more
TL;DR: In this article, the authors proposed a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages, achieving more than 60% residue amplifier power savings over a conventional implementation.
Journal ArticleDOI
A three-axis micromachined accelerometer with a CMOS position-sense interface and digital offset-trim electronics
M. Lemkin,Bernhard E. Boser +1 more
TL;DR: In this paper, the authors describe a three-axis accelerometer implemented in a surface-micromachining technology with integrated CMOS, which measures changes in a capacitive half-bridge to detect deflections of a proof mass, which result from acceleration input.
Journal ArticleDOI
MOS charge pumps for low-voltage operation
Jieh-Tsorng Wu,Kuen-Long Chang +1 more
TL;DR: In this article, a 1.2-V-to-3.5-V charge pump and a 2-V to 16-V voltage pump are demonstrated. But the limitation imposed by the diode-configured output stage can be mitigated by pumping it with a clock of enhanced voltage amplitude.
References
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A 10-b 20-Msample/s analog-to-digital converter
TL;DR: In this paper, a 10-b 20-Msample/s analog-to-digital converter fabricated in a 0.9-mu m CMOS technology is described, which uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a SNDR of 60 dB with a full-scale sinusoidal input at 5 MHz.
Journal ArticleDOI
A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS
Y.-M. Lin,B. Kim,Paul R. Gray +2 more
TL;DR: A self-calibrated pipelined A/D converter technique potentially appropriate for high-resolution video applications that requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques.
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An experimental 1.5-V 64-Mb DRAM
Y. Nakagome,Tanaka Haruhiko,Kan Takeuchi,E. Kume,Y. Watanabe,Toru Kaga,Yoshifumi Kawamoto,Fumio Murai,R. Izawa,Digh Hisamoto,T. Kisu,Takashi Nishida,Eiji Takeda,K. Itoh +13 more
TL;DR: In this paper, an accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed to reduce data transmission delay.
Journal ArticleDOI
A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC
TL;DR: Two new circuit techniques, termed pipelined capacitive interpolation and error averaging circuits with capacitor networks, are developed, which result in very low power dissipation at a low power-supply voltage at the conversion frequency.
Proceedings ArticleDOI
A 95 mW, 10 b 15 MHz low-power CMOS ADC using analog double-sampled pipelining scheme
TL;DR: In this paper, a very low power, 95 mW, 10 b 15 MHz CMOS pipelined fully differential A/D converter (ADC) is fabricated using analog double sampling.