Journal ArticleDOI
Differential CMOS edge-triggered flip-flop based on clock racing
Y. Moisiadis,I. Bouras +1 more
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TLDR
In this paper, a differential CMOS edge-triggered flip-flop is proposed that employs a pair of cross-coupled inverters, providing fully static operation.Abstract:
A differential CMOS edge-triggered flip-flop is proposed that employs a pair of cross-coupled inverters, providing fully static operation. The edge-triggering operation is achieved by a narrow pulse, produced by the clock signal and its inverted delayed version. The proposed flip-flop exhibits significant power savings of up to 25%, when compared with other static differential flip-flop circuits, maintaining its speed advantage for different power supply voltages and data activity rates. It also requires only 12 transistors resulting in a reduced transistor count. Moreover, unlike the existing differential circuits, it has the ability to operate under a reduced swing clock signal, without static power dissipation.read more
Citations
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Journal ArticleDOI
Differential CMOS edge-triggered flip-flop with clock-gating
Yinshui Xia,A.E.A. Almaini +1 more
TL;DR: A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops and shows that compared to a recently published design the proposed circuit can save power when switching activity of the input signal <0.65.
Journal ArticleDOI
Analysis of High-Performance Flip-Flops for Submicron Mixed-Signal Applications
TL;DR: In this article, a detailed analysis of high-performance edge-triggered memory elements for deep submicron mixed-signal applications is presented, where the variations of the main parameters (power, delay, peak of supply current) with supply voltage, as well as timing restrictions have been studied.
Patent
Latch circuit and clock signal dividing circuit
TL;DR: In this paper, a difference detector is coupled to a D-type latch, and has a difference output that provides a difference signal when data at input is different than data at output, and the difference signal is provided to gate control input.
Journal ArticleDOI
Low-power pulsed hybrid flip-flop based on a C-element
Majid Rahiminejad,Mohsen Saneei +1 more
TL;DR: In this article, a hybrid flip-flop design with implicit pulse-triggered structure is presented, in which a dynamic front-end stage and a static back-end one are adopted.
Proceedings ArticleDOI
Analysis and design of level-converting flip-flops for dual-V/sub dd//V/sub th/ integrated circuits
R. Bai,Dennis Sylvester +1 more
TL;DR: This paper proposes two novel designs and extends two previous non-level-converting flip-flops to intrinsically perform level conversion and shows delay improvement of up to 50% and energy-delay product reductions of 15-50% compared to a conventional level- Converting master-slave Flip-flop.
References
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Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Journal ArticleDOI
New single-clock CMOS latches and flipflops with improved speed and power savings
Jiren Yuan,Christer Svensson +1 more
TL;DR: In the new differential flipflops, clock loads are minimized and logic-related transistors are purely n-type in both n- and p-latches, giving additional speed advantage to this kind of CMOS circuits.
Journal ArticleDOI
CMOS edge-triggered flip-flop using one latch
TL;DR: The authors use the narrow pulse produced by the race-hazard of the clock signal to control the latch, so as to meet the ‘non-transparent’ demand of the flip-flop.