Proceedings ArticleDOI
Dynamic cache clustering for chip multiprocessors
Mohammad Hammoud,Sangyeun Cho,Rami Melhem +2 more
- pp 56-67
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TLDR
Simulation results using a full-system simulator demonstrate that DCC outperforms alternative L2 cache designs and uniquely and efficiently optimizes both metrics and continuously tracks a near-optimal cache organization from many possible configurations.Abstract:
This paper proposes DCC (Dynamic Cache Clustering), a novel distributed cache management scheme for large-scale chip multiprocessors. Using DCC, a per-core cache cluster is comprised of a number of L2 cache banks and cache clusters are constructed, expanded, and contracted dynamically to match each core's cache demand. The basic trade-offs of varying the on-chip cache clusters are average L2 access latency and L2 miss rate. DCC uniquely and efficiently optimizes both metrics and continuously tracks a near-optimal cache organization from many possible configurations. Simulation results using a full-system simulator demonstrate that DCC outperforms alternative L2 cache designs.read more
Citations
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CloudCache: Expanding and shrinking private caches
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METE: meeting end-to-end QoS in multicores through system-wide resource management
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Proceedings ArticleDOI
HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors
TL;DR: A novel and implementable data search algorithm for D-NUCA designs in CMP architectures, called HK-N UCA (Home Knows where to find data within the NUCA cache), which exploits migration features by providing fast and power efficient accesses to data which is located close to the requesting core.
Journal ArticleDOI
Victim retention for reducing cache misses in tiled chip multiprocessors
TL;DR: Experimental evaluation using full-system simulation shows that CMP-VR has less off-chip miss-rate as compared to baseline Tiled CMP, and reduction in CPI and miss rate together guarantees performance improvement.
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Proceedings ArticleDOI
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
Sriram R. Vangal,Jason Howard,G. Ruhl,Saurabh Dighe,H. Wilson,J. Tschanz,D. Finan,P. Iyer,A. Singh,Tiju Jacob,Shailendra Jain,S. Venkataraman,Y. Hoskote,Nitin Borkar +13 more
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Journal ArticleDOI
Low-Latency Virtual-Channel Routers for On-Chip Networks
TL;DR: Simulations illustrate that dramatic cycle time improvements are possible without compromising router efficiency, and these reductions permit flits to be routed in a single cycle, maximising the effectiveness of the router's limited buffering resources.