Patent
Dynamic memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
TLDR
In this paper, a three-dimensional DRAM device with a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor where crystallization seeds are provided by the singlecrystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator.Abstract:
Dynamic random access memory (DRAM) devices are taught wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor and a fabrication method therefor wherein crystallization seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO 2 /Si 3 N 4 /SiO 2 is provided for the capacitor storage insulator. A thin layer of SiO 2 is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO 2 layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.read more
Citations
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Patent
Microstructures and single mask, single-crystal process for fabrication thereof
TL;DR: In this paper, a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation is described.
Patent
Vertical DRAM cell and method
TL;DR: In this paper, a method for forming DRAM cells in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during fabrication is described.
Patent
Vertical type MOS transistor and method of formation thereof
TL;DR: In this article, a vertical MOS transistor has been shown to have its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed.
Patent
Method of fabricating cross-point lightly-doped drain-source trench transistor
TL;DR: In this paper, a self-aligned, lightly-doped drain/source n-channel field effect transistor is constructed in a well region in a wafer including an epitaxial layer on a substrate.
Patent
Low temperature plasma oxidation process
David M. Dobuzinsky,David L. Harmon,Srinandan R. Kasi,Donald M. Kenney,Son V. Nguyen,Tue Nguyen,Pai-Hung Pan +6 more
TL;DR: In this article, a process for forming a thin film on a surface of a semiconductor device is described. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1.
References
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Patent
Silicon integrated circuits
TL;DR: In this article, a dynamic random access memory (DRAM) is proposed in which individual cells, including an access transistor and a storage capacitor, are formed in mesas formed on a silicon chip.
Patent
Manufacture of semiconductor device
TL;DR: In this article, the authors proposed a method to restore a crystal defect by ion implantation at a heat-treatment temperature by a method wherein, in a heat treatment method used to restore the crystal defect, implanting impurity ions into a compound semiconductor provided with a heterostructure, a composition ratio of elements constituting a first semiconductor layer is set to a value by which a lattice constant of the first layer nearly coincides with the lattice constants of a second layer, and when it is lattice-matched at the heat treatment temperature in this manner, a
Patent
Fet memory cell structure and process
TL;DR: In this article, a dense, vertical MOS FET memory cell has a high charge storage capacitance per unit area of substrate surface and charge storage capacitor structure is formed within a well etched in the silicon semiconductor substrate by a combination of reactive ion etching and a self-limiting wet etch.
Patent
Method of manufacturing semiconductor devices
Hiroshi Iwai,Yoshio Nishi +1 more
TL;DR: In this article, a method of manufacturing semiconductor devices is described, which comprises the steps of: forming at least one groove at a given location of a semiconductor substrate, laying an insulating film over the entire surface of the substrate including the groove, depositing conductive material on the insulating layer to a thickness greater than half the width of an opening of the groove; and forming a MOS capacitor electrode of the conductor layer left in the groove by etching the deposited conductor layer until the insulator film other than its portion within the groove is exposed.
Patent
Fabrication of dielectrically isolated microelectronic semiconductor circuits utilizing selective growth by low pressure vapor deposition
TL;DR: In this article, a method for the fabrication of microelectronic semiconductor circuits, including the concurrent low pressure deposition of monocrystalline and polycrystalline semiconductor material in a predetermined pattern, is described.