Journal ArticleDOI
Early Analysis of Fault-based Attack Effects in Secure Circuits
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TLDR
This paper discusses the similarities and differences between the two types of application areas and proposes extensions of the classical fault models to cover security-related constraints and Experimental results on a coprocessor for RSA encryption demonstrate the need for such an extended fault model.Abstract:
Security often relies on functions implemented in hardware. But, various types of attacks have been developed, in particular, fault-based attacks allowing a hacker to observe abnormal behaviors from which secret data can be inferred. Analyzing very early, during a circuit design, the potential impact of faults therefore becomes necessary to avoid security flaws. Dependability analysis environments have been developed to analyze the effect of "natural" faults, for example, those induced by particles. This paper discusses the similarities and differences between the two types; of application areas and proposes extensions of the classical fault models to cover security-related constraints. Experimental results on a coprocessor for RSA encryption demonstrate the need for such an extended fault model.read more
Citations
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Proceedings ArticleDOI
Fault Injection Resilience
TL;DR: This paper illustrates two families of fault injection resilience (FIR) schemes suitable for symmetric encryption, and details how a countermeasure of this later family can both protect both against active and passive attacks, thereby bringing a combined global protection of the device.
Proceedings ArticleDOI
A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks
TL;DR: This work involves the development of an RTL fault injection approach more representative of laser attacks than random multi-bit fault injections and the utilization and evolution of state of the art emulation techniques to reduce the duration of the fault injection campaigns.
Proceedings ArticleDOI
A bulk built-in sensor for detection of fault attacks
TL;DR: This work presents a novel scheme of built-in current sensor (BICS) for detecting transient fault-based attacks of short and long duration as well as from different simultaneous sources.
Journal ArticleDOI
Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode
Rodrigo Possamai Bastos,Frank Sill Torres,Giorgio Di Natale,Marie-Lise Flottes,Bruno Rouzeyre +4 more
TL;DR: A novel circuit for detecting transient faults in combinational and sequential logic featuring a built-in current sensor connected to the bulks of the monitored logic and enhanced with low-power sleep-mode is presented.
Proceedings ArticleDOI
Modular Fault Injector for Multiple Fault Dependability and Security Evaluations
TL;DR: A new in-system fault injection strategy for automatic test pattern injection is introduced and an approach is presented that provides an abstraction of the internal fault injection structures to a more generic high level view.
References
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Memo on RSA signature generation in the presence of faults
TL;DR: This research presents a novel probabilistic procedure called “spot-spot analysis” that allows for real-time analysis of the response of the immune system to foreign substance abuse.
Proceedings ArticleDOI
New Techniques for Speeding-Up Fault-Injection Campaigns
L. Berrojo,I. Gonzalez,Fulvio Corno,Matteo Sonza Reorda,Giovanni Squillero,Luis Entrena,C. Lopez +6 more
TL;DR: Experimental results are provided, showing the effects of the different techniques, and demonstrating that they are able to reduce the total time required by fault-injection campaigns by at least one order of magnitude.
Proceedings ArticleDOI
Comparison and application of different VHDL-based fault injection techniques
TL;DR: Compares different VHDL-based fault injection techniques: simulator commands, saboteurs and mutants for the validation of fault tolerant systems and preliminary results show that coverages for transient faults can be obtained quite accurately with any of the three techniques.
Proceedings ArticleDOI
New methods for evaluating the impact of single event transients in VDSM ICs
TL;DR: In this paper, a SET (single event transient) fault simulation technique is proposed to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell.
Journal ArticleDOI
Multi-Level Fault Injections in VHDL Descriptions: Alternative Approaches and Experiments
Regis Leveugle,K. Hadjiat +1 more
TL;DR: Results show that an analysis performed at a very early stage in the design process can actually give a helpful insight into the response of a circuit when a fault occurs, and in the proposed analysis flow, a behavioural model is generated.