Proceedings ArticleDOI
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature
Takafumi Fukushima,E. Iwata,Jichoel Bea,M. Murugesan,K. W. Lee,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
- pp 1-5
TLDR
A new chip-to-wafer 3D integration using self-assembly by which many KGDs can be simultaneously, rapidly, and precisely aligned and tightly bonded on wafers is proposed.Abstract:
Chip-to-wafer bonding is a promising technology for 3D integration due to high production yield using known good dies (KGDs). However, conventional chip-to-wafer 3D integration lowers production throughput because pick-and-place chip assembly is employed. To overcome the problem, we proposed a new chip-to-wafer 3D integration using self-assembly by which many KGDs can be simultaneously, rapidly, and precisely aligned and tightly bonded on wafers. The driving force is liquid surface tension. Here, we used an aqueous solution including dilute HF. In this paper, we discuss the dependence of alignment accuracy on several parameters in self-assembly conditions. In addition, we describe mechanism on HF-assisted direct chip bonding to wafers without thermal compression.read more
Citations
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Journal ArticleDOI
3-D Integration and Through-Silicon Vias in MEMS and Microsensors
TL;DR: The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics as discussed by the authors.
Journal ArticleDOI
Post-CMOS Processing and 3-D Integration Based on Dry-Film Lithography
TL;DR: In this paper, a chip-level post-complementary metal oxide semiconductor (CMOS) processing technique for 3D integration and through-silicon-via (TSV) fabrication is presented.
Proceedings ArticleDOI
Impact of containment and deposition method on sub-micron chip-to-wafer self-assembly yield
TL;DR: This paper will focus on chip-to-wafer self assembly processes coupled with direct bonding hybridation, and submicronic alignment accuracy and a 90 per cent self-assembly process yield are obtained.
Journal ArticleDOI
15-µm-pitch Cu/Au interconnections relied on self-aligned low-temperature thermosonic flip-chip bonding technique for advanced chip stacking applications
TL;DR: In this article, the authors report the development of reliable fine-pitch micro bump interconnections that used a high-precision room-temperature bonding approach, which improved the accuracy of the bonding process by modifying conventional bump/planar-bonding-pad Interconnections to form self-aligned micro bumps/truncated inverted pyramid (TIP) bonding pads.
Proceedings ArticleDOI
A CMOS-compatible chip-to-chip 3D integration platform
TL;DR: In this article, a CMOS compatible chip-to-chip 3D integration platform is presented, which allows reconstituting a wafer from diced and thinned chips.
References
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TL;DR: In this work, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using a new three-dimensional integration technology to overcome future wiring connectivity crises.
Journal ArticleDOI
High-Density Through Silicon Vias for 3-D LSIs
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TL;DR: In this paper, a polycrystalline silicon (poly-Si) TSV technology and tungsten (W)/poly poly-Si TSV for 3D integration was developed.
Journal ArticleDOI
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
Mitsumasa Koyanagi,T. Nakamura,Yusuke Yamada,H. Kikuchi,Takafumi Fukushima,Tetsu Tanaka,Hiroyuki Kurino +6 more
TL;DR: In this article, a 3D shared-memory test chip with three-stacked layers was fabricated by bonding the wafers with vertical buried interconnections after thinning.
Proceedings ArticleDOI
New three-dimensional integration technology using self-assembly technique
TL;DR: In this article, a 3D SRAM test chip with ten memory layers was successfully fabricated using the super-smart-stack (SSS) technology using a self-assembly technique.