Proceedings ArticleDOI
Fault Dictionary Based Scan Chain Failure Diagnosis
Ruifeng Guo,Yu Huang,Wu-Tung Cheng +2 more
- pp 45-52
TLDR
In this paper, a fault dictionary based scan chain failure diagnosis technique is presented, which is up to 130 times faster with the same level of diagnosis accuracy and resolution compared with fault simulation based diagnosis technique.Abstract:
In this paper, we present a fault dictionary based scan chain failure diagnosis technique. We first describe a technique to create small dictionaries for scan chain faults by storing differential signatures. Based on the differential signatures stored in a fault dictionary, we can quickly identify single stuck-at fault or timing fault in a faulty chain. We further develop a novel technique to diagnose some multiple stuck-at faults in a single scan chain. Comparing with fault simulation based diagnosis technique, the proposed fault dictionary based diagnosis technique is up to 130 times faster with same level of diagnosis accuracy and resolution.read more
Citations
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Journal ArticleDOI
Survey of Scan Chain Diagnosis
TL;DR: A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks, and the purpose of chain patterns is to test scan chain integrity.
Proceedings ArticleDOI
Built-in self-test for micro-electrode-dot-array digital microfluidic biochips
TL;DR: The proposed BIST architecture can effectively detect defects in a MEDA biochip, and faulty microcells can be identified, and simulation results based on HSPICE and experiments using fabricated MEDABiochips highlight the effectiveness of the proposed Bist architecture.
Journal ArticleDOI
Structural and Functional Test Methods for Micro-Electrode-Dot-Array Digital Microfluidic Biochips
TL;DR: This paper presents the first approach for testing of MEDA biochips that include both CMOS circuits and microfluidic components, and presents structural test techniques to evaluate the pass/fail status of each microcell and identify faulty microcells.
Patent
Test failure bucketing
TL;DR: In this article, failure messages generated as a result of tests performed on a target application are bucketed in an effort to correlate related failure messages with minimal or no human interaction, which is called bucketing failure messages.
Patent
Method for recognising sequential patterns for a method for fault message processing
Nicolas Schneider,Sylvie Delprat +1 more
TL;DR: In this article, a method for processing a sequence of fault messages occurring in an apparatus including numerous systems, that makes it possible to discriminate fault messages most likely originating from a real system fault and fault messages without any real fault of the associated system (no fault found), is presented.
References
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Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI
Embedded deterministic test
TL;DR: This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Proceedings ArticleDOI
Embedded deterministic test for low cost manufacturing test
Janusz Rajski,Jerzy Tyszer,M. Kassab,Nilanjan Mukherjee,Rob Thompson,Kun-Han Tsai,A. Hertwig,Nagesh Tamarapalli,Grzegorz Mrugalski,Geir Eide,Jun Qian +10 more
TL;DR: Embedded deterministic test technology is introduced, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time.
Journal ArticleDOI
Failure diagnosis of structured VLSI
J.A. Waicukauski,E. Lindbloom +1 more
TL;DR: The authors describe a method for diagnosing the failures observed in testing VLSI designs that use the scan-path structure by simulating selected faults after testing using a fault simulator that allows the application of several patterns in parallel.
Proceedings ArticleDOI
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm
TL;DR: A new way of diagnosing ICs that fail logic tests is described, which can handle bridging fault, opens, transition faults and many more complex defects as easily and as accurately as regular stuck-at faults.