Journal ArticleDOI
Field programmable gate arrays and floating point arithmetic
Barry Fagin,C. Renard +1 more
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An assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.Abstract:
We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic. >read more
Citations
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Proceedings ArticleDOI
An efficient implementation of floating point multiplier
TL;DR: An efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA using VHDL to implement a technology-independent pipelined design.
Proceedings ArticleDOI
Handling different computational granularity by a reconfigurable IC featuring embedded FPGAs and a network-on-chip
F. Lertora,M. Borgatti +1 more
TL;DR: A system-on-chip integrating a microprocessor, three embedded FPGA (eFPGA) and an eight port network- on-chip (NoC) is implemented in a 90nm CMOS technology to execute complex multimedia applications by the use of hardware accelerators mapped to a reconfigured platform based on a message-passing architecture.
Proceedings ArticleDOI
A comparison of floating point and logarithmic number systems for FPGAs
Michael Haselman,M.J. Beauchamp,Aaron Wood,Scott Hauck,Keith D. Underwood,Karl Scott Hemmert +5 more
TL;DR: This work created a parameterized LNS library of computational units and compared them to an existing floating point library, considered multiplication, division, addition, subtraction, and format conversion to determine when one format should be used over the other and when it is advantageous to change formats during a calculation.
Book ChapterDOI
Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine
TL;DR: By implementing the FFT algorithm on a custom computing machine (CCM) called Splash-2, a computation speed of 180 Mflops and a speed-up of 23 times over a Sparc-10 workstation is achieved.
Proceedings ArticleDOI
Advanced Components in the Variable Precision Floating-Point Library
TL;DR: The authors recently added three advanced components:floating-point division, floating-point square root and floating- point accumulation to their library, which can be used to achieve more parallelism and less power dissipation than adhering to a standard format.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
An architecture for electrically configurable gate arrays
TL;DR: An architecture for electrically configurable gate arrays using a two-terminal antifuse element is described, and can provide a level of integration comparable to mask-programmable gate arrays.
Journal ArticleDOI
A Proposed Standard for Binary Floating-Point Arithmetic
TL;DR: This proposed standard facilitates transportation of numerically oriented programs and encourages development of high-quality numerical software.
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