Journal ArticleDOI
Field programmable gate arrays and floating point arithmetic
Barry Fagin,C. Renard +1 more
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An assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic.Abstract:
We present empirical results describing the implementation of an IEEE Standard 754 compliant floating-point adder/multiplier using field programmable gate arrays. The use of FPGA's permits fast and accurate quantitative evaluation of a variety of circuit design tradeoffs for addition and multiplication. PPGA's also permit accurate assessments of the area and time costs associated with various features of the IEEE floating-point standard, including rounding and gradual underflow. These costs are analyzed, along with the effects of architectural correlation, a phenomenon that occurs when the cost of combining architectural features exceeds the sum of separate implementation. We conclude with an assessment of the strengths and weaknesses of using FPGA's for floating-point arithmetic. >read more
Citations
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Journal ArticleDOI
Floating-point scaling technique for sources separation automatic gain control
TL;DR: This work proposes a scaling technique applied to the separation matrix, to avoid the saturation or the weakness in the recovered source signals and demonstrates the effectiveness of this technique by using the implementation of a division-free BSS algorithm with two inputs, two outputs.
Proceedings ArticleDOI
Comparing throughput and power consumption in both sequential and reconfigurable processors
TL;DR: A high-level language (HLL)-Mitrion-C 1.4 is used to implement on an FPGA two computations taken from a ray-tracing simulation, achieving a 10times speedup using FPGAs over sequential processors at a cost of 1.3times the power.
Journal ArticleDOI
Implementation of Double Precision FloatingPoint Multiplier on FPGA
A.Keerthi,K.V.Koteswararao +1 more
TL;DR: The proposed design is an implementation of an IEEE-754 Double Precision Floating Point Multiplier, which is better when compared to a single precision multiplier because of its wider dynamic ranges and accuracy.
Proceedings ArticleDOI
Design of parallel vector/scalar floating point co-processor for reconfigurable architecture
TL;DR: This research has implemented a high performance, autonomous floating point vector co-processor (FPVC) that works independently within an embedded processor system, and presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements.
References
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Book
Computer Architecture: A Quantitative Approach
TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.
Journal ArticleDOI
An architecture for electrically configurable gate arrays
TL;DR: An architecture for electrically configurable gate arrays using a two-terminal antifuse element is described, and can provide a level of integration comparable to mask-programmable gate arrays.
Journal ArticleDOI
A Proposed Standard for Binary Floating-Point Arithmetic
TL;DR: This proposed standard facilitates transportation of numerically oriented programs and encourages development of high-quality numerical software.
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