High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs

TLDR: This paper proposes a high-level estimation methodology for area and performance parameters of regular FPGA designs to be found in multimedia, telecommunications or cryptography and presents the estimation approach as well as evaluation results that prove the suitability of the proposed estimation approach.

Abstract: Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercially affordable. These trends make FPGAs an alternative in application areas where extensive data processing plays an important role. Consequently, the desire emerges for early performance estimation in order to quantify the FPGA approach and to compare it with traditional alternatives. In this paper, we propose a high-level estimation methodology for area and performance parameters of regular FPGA designs to be found in multimedia, telecommunications or cryptography. The goal is to provide a means that allows early quantification of an FPGA design and that enables early trade-off considerations. We present our estimation approach as well as evaluation results, which are based on several implemented applications and prove the suitability of the proposed estimation approach.