Patent
High voltage field effect transistors
Han Wui Then,Chau Robert,Benjamin Chu-Kung,Dewey Gilbert,Jack T. Kavalieros,Matthew V. Metz,Niloy Mukherjee,Ravi Pillarisetty,Marko Radosavljevic +8 more
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TLDR
In this article, the authors defined a longitudinal length of a nanowire, defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region was disposed between the channel and drain region.Abstract:
Transistors suitable for high voltage and high frequency operation. A nanowire is disposed vertically or horizontally on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first semiconductor material, a source region electrically coupled with a first end of the channel region, a drain region electrically coupled with a second end of the channel region, and an extrinsic drain region disposed between the channel region and drain region. The extrinsic drain region has a wider bandgap than that of the first semiconductor. A gate stack including a gate conductor and a gate insulator coaxially wraps completely around the channel region, drain and source contacts similarly coaxially wrap completely around the drain and source regions.read more
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Multi-Gate Device and Method of Fabrication Thereof
TL;DR: A semiconductor includes a first transistor and a second transistor as mentioned in this paper, and a metal gate layer surrounding the first gate dielectric layer, formed of a first semiconductor material.
Patent
Group III-N nanowire transistors
Han Wui Then,Chau Robert,Benjamin Chu-Kung,Dewey Gilbert,Jack T. Kavalieros,Matthew V. Metz,Niloy Mukherjee,Ravi Pillarisetty,Marko Radosavljevic +8 more
TL;DR: In this paper, a group III-N nanowire is disposed on a substrate and a longitudinal length of the nanowires is defined into a channel region of a first group IIIN material, a source region electrically coupled with a first end of the channel region, and a drain region was connected with a second end of channel region.
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Horizontal gate-all-around device having wrapped-around source and drain
TL;DR: In this paper, the authors proposed a method of forming a semiconductor device by extending a fin extending from a substrate, where the first semiconductor layer has a first composition and the second has a second composition different from the first composition.
Patent
Methods of forming nanowire devices with doped extension regions and the resulting devices
TL;DR: In this paper, a method of patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces was proposed, and after forming the doped extension regions, forming epi semiconductor materials in source and drain regions of the device.
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Techniques for forming vertical transistor architectures
Kimin Jun,Patrick Morrow +1 more
TL;DR: In this paper, a semiconductor layer is disposed over a lower interconnect layer and patterned into a plurality of vertical semiconductor bodies (e.g., nanowires and/or other three-dimensional semiconductor structures) in a regular, semi-regular, or irregular array, as desired for a given target application or end-use.
References
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Patent
Large-area nanoenabled macroelectronic substrates and uses therefor
Xiangfeng Duan,Chunming Niu,Stephen Empedocles,Linda T. Romano,Jian Chen,Vijendra Sahi,Lawrence Bock,David P. Stumbo,J. Wallace Parce,Jay L. Goldman +9 more
TL;DR: In this article, a thin film of nanowires is formed on a substrate, and contacts are formed at the semiconductor device regions to provide electrical connectivity to the plurality of semiconductor devices.
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Nanostructures and methods for manufacturing the same
Lars Samuelson,Björn Ohlsson +1 more
TL;DR: In this article, a resonant tunneling diode and other one dimensional electronic, photonic structures, and electromechanical MEMS devices are formed as a heterostructure in a nanowhisker by forming length segments of the whisker with different materials having different band gaps.
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Field-effect transistor, circuit configuration and method of fabricating a field-effect transistor
TL;DR: The gate region of a field effect transistor comprises at least one through hole wherein a nanoelement is provided which is electrically coupled to the source and the drain this paper, and the conductance thereof is controlled by means of the gate.