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Journal ArticleDOI

Impact of Different Gate Dielectric Materials on Analog/RF Performance of Dielectric-Pocket Double Gate-All-Around (DP − DGAA) MOSFETs

Vaibhav Purwar, +3 more
- 27 Jan 2022 - 
- Vol. 14, Iss: 15, pp 9361-9366
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This article is published in Silicon.The article was published on 2022-01-27. It has received 4 citations till now. The article focuses on the topics: Gate dielectric & Dielectric.

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Journal ArticleDOI

Comparative Performance Analysis of Dual Material-Dielectric Pocket-Nano Tube (DM-DP-NT) & Dual Material-Nano Tube (DM-NT) MOSFETs

TL;DR: In this article , the performance of dual material-Dielectric pocket-Nano Tube (DM-DP-NT) MOSFET with dual material nano-tube (DMNT) was compared with DM-NT MOSFLET.
Journal ArticleDOI

Temperature dependent performance analysis of high-K dielectric pocket-double cylindrical surrounding gate (HKG-DP-DCSG) & high K-dual material- double cylindrical surrounding gate (HKG-DM-DCSG) MOSFETs

TL;DR: In this article , the authors compared the temperature-dependent performance analysis of high-K dielectric pocket-Double Cylindrical Surrounding Gate (HKG-DP-DCSG) and high-k-Dual material- double cylindrical surrounding gate (HG-DM-CSG) MOSFETs.
Proceedings ArticleDOI

Performance Evaluation of Dual-Metal (DM) Dielectric-Pocket (DP) Nanotube MOSFETs at Extreme Temperature Conditions

TL;DR: In this article , the performance of Nanotube (NT) MOSFETs was improved by using three performance booster techniques: a dielectric pocket (DP) equipped channel degrades the off-state current (Ioff), a high-k DPG and a dual-metal gate approach to improve immunity towards short channel effects (SHEs).
Proceedings ArticleDOI

Assessment of hot carrier stress induced threshold voltage shift in gate-all-around MOSFETs

TL;DR: In this article , the authors present an investigation of hot-carrier stress in GAA MOSFETs under different stress conditions, which results in a leakage pathway in the gate dielectric, resulting in degradation of the device performance.
References
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Multiple-gate SOI MOSFETs

TL;DR: In this paper, the authors describe the evolution and properties of a new class of MOSFETs, called triple-plus (3 + )-gate devices, which offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOS-FET.
Journal ArticleDOI

Considerations for Ultimate CMOS Scaling

TL;DR: Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architecture such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted.
Book

Modern Semiconductor Devices for Integrated Circuits

Chenming Hu
TL;DR: In this article, the authors proposed a band model for quantitative analysis of semiconductors, which can be used to obtain the energy gap, E-K diagrams allowing the determination of e ective masses, analysis of the energy levels with in the gap and the conduction/valence bands etc.
Journal ArticleDOI

Multi-gate SOI MOSFETs

TL;DR: In this paper, the authors describe the evolution of the SOI MOSFET from single-gate structures to multigate (double-gate, trigate, p-gate and gate-all-around) structures.
Journal ArticleDOI

Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits.

TL;DR: The proposed silicon nanotube field effect transistor offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow.
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