Journal ArticleDOI
Multiple-gate SOI MOSFETs
TLDR
In this paper, the authors describe the evolution and properties of a new class of MOSFETs, called triple-plus (3 + )-gate devices, which offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOS-FET.Abstract:
In an ever increasing need for higher current drive and better short-channel characteristics, silicon-on-insulator MOS transistors are evolving from classical, planar, single-gate devices into three-dimensional devices with multiple gates (double-, triple- or quadruple-gate devices). The evolution and the properties of such devices are described and the emergence of a new class of MOSFETs, called triple-plus (3 + )-gate devices offer a practical solution to the problem of the ultimate, yet manufacturable, silicon MOSFET.read more
Citations
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Journal ArticleDOI
Electronics and optoelectronics of two-dimensional transition metal dichalcogenides.
TL;DR: This work reviews the historical development of Transition metal dichalcogenides, methods for preparing atomically thin layers, their electronic and optical properties, and prospects for future advances in electronics and optoelectronics.
Book
Fundamentals of Modern VLSI Devices
Yuan Taur,Tak H. Ning +1 more
TL;DR: In this article, the authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices.
Journal ArticleDOI
Two-dimensional semiconductors for transistors
TL;DR: In this article, a mathematical framework to evaluate the performance of FETs and describe the challenges for improving the performances of short-channel FET in relation to the properties of 2D materials, including graphene, transition metal dichalcogenides, phosphorene and silicene.
Journal ArticleDOI
Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors
TL;DR: In the current generation of transistors, the transistor dimensions have shrunk to such an extent that the electrical characteristics of the device can be markedly degraded, making it unlikely that the exponential decrease in transistor size can continue.
Journal ArticleDOI
Performance estimation of junctionless multigate transistors
Chi-Woo Lee,Isabelle Ferain,Aryan Afzalian,Ran Yan,Nima Delidashti Akhavan,Pedrarn Razavi,Jean-Pierre Colinge +6 more
TL;DR: In this paper, the authors describe the simulation of the electrical characteristics of a new transistor concept called the junctionless multigate field effect transistor (MuGFET), which has no junctions, a simpler fabrication process, less variability and better electrical properties than classical inversionmode devices with PN junctions at the source and drain.
References
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Journal ArticleDOI
Scaling the Si MOSFET: from bulk to SOI to bulk
R.-H. Yan,Abbas Ourmazd,K.F. Lee +2 more
TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Journal ArticleDOI
Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
TL;DR: The double-gate control of silicon-on-insulator (SOI) transistors is used to force the whole silicon film (interface layers and volume) in strong inversion as discussed by the authors.
Journal ArticleDOI
Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's
C.P. Auth,James D. Plummer +1 more
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Journal ArticleDOI
Scaling theory for double-gate SOI MOSFET's
TL;DR: In this paper, a scaling theory for double-gate SOI MOSFETs is presented, which gives guidance for device design that maintains a sub-threshold factor for a given gate length.
Journal ArticleDOI
High performance fully-depleted tri-gate CMOS transistors
Brian S. Doyle,Suman Datta,Mark Beaverton Doczy,Scott Hareland,B. Jin,Jack Portland Kavalieros,Thomas D. Linton,Anand Portland Murthy,Rafael Rios,R. Chau +9 more
TL;DR: Fully depleted tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated in this article, where the transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages.