In-Datacenter Performance Analysis of a Tensor Processing Unit
Norman P. Jouppi,Cliff Young,Nishant Patil,David A. Patterson,Gaurav Agrawal,Raminder Bajwa,Sarah Bates,Suresh Bhatia,Nan Boden,Albert T. Borchers,Rick Boyle,Pierre-luc Cantin,Clifford Chao,Christopher Aaron Clark,Jeremy Coriell,Michael J. Daley,Matt Dau,Jeffrey Dean,Ben Gelb,Tara Vazir Ghaemmaghami,Rajendra Gottipati,William John Gulland,Robert Hagmann,C. Richard Ho,Doug Hogberg,John Hu,Robert Hundt,D. Hurt,Julian Ibarz,Aaron Jaffey,Alek Jaworski,Alexander Kaplan,Khaitan Harshit,Daniel Killebrew,Andy Koch,Naveen Kumar,Steve Lacy,James Laudon,James Law,Diemthu Le,Chris Leary,Zhuyuan Liu,Kyle Lucke,Alan Lundin,Gordon MacKean,Adriana Maggiore,Maire Mahony,Kieran Miller,Rahul Nagarajan,Ravi Narayanaswami,Ray Ni,Kathy Nix,Thomas Norrie,Mark Omernick,Narayana Penukonda,Andrew Everett Phelps,Jonathan Ross,Matt Ross,Amir Salek,Emad Samadiani,Chris Severn,Gregory Sizikov,Matthew Snelham,Jed Souter,Dan Steinberg,Andy Swing,Mercedes Tan,Gregory Michael Thorson,Bo Tian,Horia Toma,Erick Tuttle,Vijay K. Vasudevan,Richard Walter,Walter Wang,Eric Wilcox,Doe Hyun Yoon +75 more
- Vol. 45, Iss: 2, pp 1-12
TLDR
The Tensor Processing Unit (TPU) as discussed by the authors is a custom ASIC deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN) using a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS).Abstract:
Many architects believe that major improvements in cost-energy-performance must now come from domain-specific hardware. This paper evaluates a custom ASIC---called a Tensor Processing Unit (TPU) --- deployed in datacenters since 2015 that accelerates the inference phase of neural networks (NN). The heart of the TPU is a 65,536 8-bit MAC matrix multiply unit that offers a peak throughput of 92 TeraOps/second (TOPS) and a large (28 MiB) software-managed on-chip memory. The TPU's deterministic execution model is a better match to the 99th-percentile response-time requirement of our NN applications than are the time-varying optimizations of CPUs and GPUs that help average throughput more than guaranteed latency. The lack of such features helps explain why, despite having myriad MACs and a big memory, the TPU is relatively small and low power. We compare the TPU to a server-class Intel Haswell CPU and an Nvidia K80 GPU, which are contemporaries deployed in the same datacenters. Our workload, written in the high-level TensorFlow framework, uses production NN applications (MLPs, CNNs, and LSTMs) that represent 95% of our datacenters' NN inference demand. Despite low utilization for some applications, the TPU is on average about 15X -- 30X faster than its contemporary GPU or CPU, with TOPS/Watt about 30X -- 80X higher. Moreover, using the CPU's GDDR5 memory in the TPU would triple achieved TOPS and raise TOPS/Watt to nearly 70X the GPU and 200X the CPU.read more
Citations
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Proceedings ArticleDOI
7.2 A 12nm Programmable Convolution-Efficient Neural-Processing-Unit Chip Achieving 825TOPS
Yang Jiao,Liang Han,Rong Jin,Yi-Jung Su,Chiente Ho,Li Yin,Yun Li,Long Chen,Zhen Chen,Lu Liu,Zhuyu He,Yu Yan,Jun He,Jun Mao,Xiaotao Zai,Xuejun Wu,Yongquan Zhou,Mingqiu Gu,Guocai Zhu,Rong Zhong,Wenyuan Lee,Ping Chen,Yiping Chen,Weiliang Li,Deyu Xiao,Qing Yan,Mingyuan Zhuang,Jiejun Chen,Yun Tian,Yingzi Lin,Wei Wu,Hao Li,Dou Zesheng +32 more
TL;DR: This NPU is architected to be CONV-efficient under the control of operation-fused coarse-grained instructions that integrates as much computing power as possible via squeezed computation with a large SRAM-only design and delivers programming flexibility via an instruction set architecture with coverage for anticipated forward-looking functionality.
Proceedings ArticleDOI
DNNGuard: An Elastic Heterogeneous DNN Accelerator Architecture against Adversarial Attacks
TL;DR: DNNGuard is proposed, an elastic heterogeneous DNN accelerator architecture that can efficiently orchestrate the simultaneous execution of original (target) DNN networks and the detect algorithm or network that detects adversary sample attacks, and is implemented based on RISC-V and NVDLA.
Proceedings ArticleDOI
On-chip deep neural network storage with multi-level eNVM
TL;DR: This paper proposes a method to use multi-level, embedded nonvolatile memory (eNVM) to eliminate all off-chip weight accesses, and co-design the weights and memories such that their properties complement each other and the faults result in no noticeable NN accuracy loss.
Proceedings ArticleDOI
Accelerating TensorFlow with Adaptive RDMA-Based gRPC
TL;DR: This paper proposes a unified approach to have a single gRPC runtime in TensorFlow with Adaptive and efficient RDMA protocols, and proposes designs such as hybrid communication protocols, message pipelining and coalescing, zero-copy transmission etc to make the runtime be adaptive to different message sizes for Deep Learning workloads.
Journal ArticleDOI
A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons
TL;DR: A scalable architecture to simulate a randomly connected network of Hodgkin-Huxley neurons is presented, in which each core can update the states of a group of neurons stored in its corresponding memory bank through a novel method of cyclic permutation of a single prestored connectivity vector per core.
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TL;DR: This best-selling title, considered for over a decade to be essential reading for every serious student and practitioner of computer design, has been updated throughout to address the most important trends facing computer designers today.