Journal ArticleDOI
Integrating online and offline testing of a switching memory
TLDR
A circuit used in a telephone switching unit features several test techniques, including BIST, partial scan, and boundary scan, which minimizes additional logic while achieving very high fault coverage.Abstract:
A circuit used in a telephone switching unit features several test techniques, including BIST, partial scan, and boundary scan. By sharing the same circuitry for both online and offline testing, the design minimizes additional logic while achieving very high fault coverage.read more
Citations
More filters
Journal ArticleDOI
Testing and build-in self-test - a survey
TL;DR: This survey reviews common test methods and analyzes the basic test procedure, the concept of BIST is introduced and discussed, BIST strategies for random logic as well as for structured logic are shown.
Journal ArticleDOI
Efficient online and offline testing of embedded DRAMs
TL;DR: A new technique for output data compression which offers the same benefits as signature analysis during off-line test, but also supports efficient online consistency checking is presented, which perfectly complements standard online checking approaches relying on EDC.
Proceedings ArticleDOI
Error detecting refreshment for embedded DRAMs
TL;DR: Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency), and achieves a very high error coverage at low hardware costs.
Journal ArticleDOI
Hierarchical Verification of Galois Field Circuits
TL;DR: The proposed hierarchical method for the formal hardware verification of Galois field architecture circuits has been found to lead to significant gains in time and space, depending on the resources that are available.
Journal ArticleDOI
Transparent-Test Methodologies for Random Access Memories Without/With ECC
TL;DR: A transparent-test methodology for memories with error-correction code (ECC) is also proposed, which can test and locate faulty cells, and no signature prediction is needed.
References
More filters
Book
Testing Semiconductor Memories: Theory and Practice
TL;DR: Memory modeling functional testing: reduced functional RAM chip model Functional RAM chip testing functional ROM chip testingfunctional memory array testing functional memory board testing electrical testing: parametric testing dynamic testing on chip testing conclusions: address line scrambling various proofs software package.
Journal ArticleDOI
Efficient Algorithms for Testing Semiconductor Random-Access Memories
TL;DR: A fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented and an efficient 0(n) algorithm to detect all faults in the fault model is described.
Proceedings ArticleDOI
Transparent bist for rams
TL;DR: A technique allowing to transform any RAM test algorithm to a transparent BlST algorithm which preserves the initial contents of the RAM is presented and it becomes more attractive than the standard BlST since it allows to perform both fabrication testing and periodic testing.
Journal ArticleDOI
Industrial BIST of embedded RAMs
TL;DR: The scheme implements in hardware the test pattern generation algorithm proposed by R. Nair, S.M. Thatte, and J.A. Abraham, extending it to word-based memories, and guarantees high fault coverage for the significant failure modes and full testability of the BIST hardware.
Journal ArticleDOI
Influences on soft error rates in static RAMs
P.M. Carter,B.R. Wilkins +1 more
TL;DR: Quantitative estimates of expected SER improvements are presented after various parameters in the cell model were changed in order to investigate the effects on the alpha-particle sensitivity, and the results suggest a mechanism by which the mechanism could most economically be improved.