Proceedings ArticleDOI
Junctionless transistor: a review
S. Intekhab Amin,Rakesh Kumar Sarin +1 more
- pp 432-439
TLDR
In this article, the authors proposed a junctionless transistor, which is a uniformly doped nanowire without junction and no doping concentration gradient exist, which shows better short channel effect and less degradation in mobility with temperature, small DIBL, subthreshold swing and higher voltage gain.Abstract:
This paper is based on the extensive study of a Junctionless transistor. Since the entire conventional transistor have junction, which limits it's scaling as it requires very abrupt junction, high concentration gradient and become challenging with every technology node. The problems comes when there is a junction in such a device like MOSFETs which has source junction and drain junction formed with oppositely doped substrate. A junctionless transistor is a uniformly doped nanowire without junction and no doping concentration gradient exist. It shows better short channel effect and less degradation in mobility with temperature, small DIBL, subthreshold swing and higher voltage gain which shows good scalability below 10nm and reduces the fabrication complexity. Junctionless transistor is a very promising candidate for future nano scale MOSFET device.read more
Citations
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Proceedings ArticleDOI
Investigating short channel effects and performance parameters of double gate junctionless transistor at various technology nodes
TL;DR: In this article, the short channel effects and performance parameters of double gate junctionless transistor are analyzed at different channel lengths (20nm, 25nm, and 30nm) and the reasons for variations of parameters are discussed.
Journal ArticleDOI
Analysis of Threshold Voltage and Drain Induced Barrier Lowering in Junctionless Double Gate MOSFET Using High-κ Gate Oxide
TL;DR: In this article, an analytical threshold voltage model is proposed using the first term of the series-type potential model derived from the Poisson equation, and the change of threshold voltage and Drain Induction Barrier Lowering (DIBL) is observed when high dielectric constant material is used as gate oxide of the junctionless double gate (JLDG) MOSFET.
Journal ArticleDOI
Simulation and Characterization of Junction Less CMOS Inverter at Various Technology Nodes
TL;DR: In this article, the simulation and drawing based on junction less transistor technology CMOS inverter is discussed at various channel lengths at different channel lengths and the transient curve, noise margin, various differences between conventional and junction less technology has been illustrated in this paper.
Journal ArticleDOI
Relationship of drain induced barrier lowering and top/bottom gate oxide thickness in asymmetric junctionless double gate MOSFET
TL;DR: In this article, the relationship between drain induced barrier lowering (DIBL) phenomenon and channel length, silicon thickness, and thicknesses of top and bottom gate oxide films is derived for asymmetric junctionless double gate (JLDG) MOSFETs.
Proceedings ArticleDOI
Gate Length Modulation of Junction-less Transistor Based on Silicon Nanowire
Shammy Kumar,Kartikey Solanki +1 more
TL;DR: In this article, the influence on the characteristics of Silicon Nanowire junction-less transistor (JLT) with help of PADRE MuGFET simulation tools in the situation when we vary the length of gate.