Patent
Linearity improvements of semiconductor substrate based radio frequency devices
TLDR
In this paper, a trap-rich layer, such as a polycrystalline Silicon layer over a semiconductor substrate, is used to substantially immobilize a surface conduction layer at the surface of the semiconductor substrategies at radio frequency (RF) frequencies.Abstract:
The present invention relates to using a trap-rich layer, such as a polycrystalline Silicon layer, over a semiconductor substrate to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate at radio frequency (RF) frequencies. The trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.read more
Citations
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Patent
Trap rich layer for semiconductor devices
TL;DR: In this article, an integrated circuit chip is formed with an active layer and a trap-rich layer, where the trap layer is formed above the active layer by a metal interconnect layer.
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Trap rich layer with through-silicon-vias in semiconductor devices
TL;DR: In this article, an integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias, which are also formed above the circuit layer.
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Silicon-on-plastic semiconductor device with interfacial adhesion layer
TL;DR: In this article, a semiconductor device with a polymer substrate and an interfacial adhesion layer over the polymer substrate is described, and methods for manufacturing the same are described. But the authors do not discuss the fabrication process.
Patent
Trap Rich Layer Formation Techniques for Semiconductor Devices
TL;DR: In this paper, a trap-rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer, and combinations of two or more of these techniques may be used to form a trap rich layer.
Patent
Method of manufacturing high resistivity soi wafers with charge trapping layers based on terminated si deposition
TL;DR: In this paper, a method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided, which consists of forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single-crystal semiconductor handled wafer.
References
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Journal ArticleDOI
Low-loss CPW lines on surface stabilized high-resistivity silicon
TL;DR: In this article, an LPCVD polycrystalline silicon layer is placed over the surface of a high-resistivity silicon wafer which is then covered with a silicon dioxide layer.
Journal ArticleDOI
New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity
TL;DR: In this paper, the authors proposed a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers.
Journal ArticleDOI
SiO/sub 2/ interface layer effects on microwave loss of high-resistivity CPW line
TL;DR: In this article, a coplanar waveguide (CPW) line where the metal conductor is in direct contact with the HR-Si substrate, the microwave losses are low but are sensitive to DC bias due to DC leakage current.
Patent
Radio frequency circuit with integrated on-chip radio frequency signal coupler
TL;DR: In this article, an integrated coupler is proposed to provide efficient and reproducible RF coupling without increasing the die footprint of the RF circuit, and the coupler can be used in the same substrate using the same IPD process technology.
Journal ArticleDOI
Energy distribution of trapping states in polycrystalline silicon
S. Hirae,M. Hirose,Y. Osaka +2 more
TL;DR: In this paper, the electronic density of states in the forbidden gap of polycrystalline silicon has been determined from an analysis of capacitance and conductance of a Metal/SiO2 (∼60 A)/polycrystaline silicon(∼250 A)/Si(111) (MOSS) structure.