Low Power Clock Network Design
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TLDR
Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared and metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation.Abstract:
Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation.read more
Citations
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Journal ArticleDOI
Full-Swing Gate Diffusion Input logic-Case-study of low-power CLA adder design
TL;DR: Full Swing Gate Diffusion Input (FS-GDI) methodology is presented and results show 2x area reduction, 5x improvement in dynamic energy dissipation and 4x decrease in leakage, with a slight degradation in performance when compared to the CMOS CLA.
Patent
Reducing dynamic clock skew and/or slew in an electronic circuit
TL;DR: In this article, a set of neighboring buffer pairs with active buffers and adjacent sub-meshes, which are connected by a shorting bar, are identified, and for each neighboring buffer pair of the set, placing a dummy buffer for each of their active buffers in the adjacent submeshes close to the active buffers, routing an input of a first dummy buffer located in a first sub-mesh to an output of an active buffer in a second submesh, and connecting inputs of the first and second dummy buffers to the shorting bars.
Journal ArticleDOI
A buffer placement algorithm to overcome short-circuit power dissipation in mesh based clock distribution network
TL;DR: This paper proposes a buffer placement algorithm which can overcome the short circuit power dissipated in clock meshes by using clustering technique to judiciously place buffers such that short-circuit power is minimized while minimizing skew at the same time.
Proceedings ArticleDOI
Buffer reduction algorithm for mesh-based clock distribution
TL;DR: This short paper proposes a buffer reduction algorithm which can reduce the power dissipated in clock meshes by 15-18% at the cost of 10-20 ps increase in skew when compared to the previously published work.
Proceedings ArticleDOI
Three-dimensional pipeline clock network design with multi-layer processor chip and multi-clock VLSI system
TL;DR: Experimental results can be used to prove that 3D pipeline clock network has better performance with fast operation speed and small routing length, and whole VLSI system power can be reduced because of minimal routing distance in 3D network design.
References
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