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Journal ArticleDOI

Measurements on depletion-mode field effect transistors and buried channel MOS capacitors for the characterization of bulk transfer charge-coupled devices

A.M. Mohsen, +1 more
- 01 May 1975 - 
- Vol. 18, Iss: 5, pp 407-416
TLDR
In this paper, the properties of bulk transfer charge-coupled devices (BCCDs) were characterized from measurements obtained using MOS capacitors and field effect transistors.
Abstract
The properties of bulk transfer charge-coupled devices (BCCD's) may be characterized from measurements obtained using MOS capacitors and field effect transistors. Models are presented for the MOS capacitor and field effect transistor for the case where a shallow doped layer of polarity opposite to that of the substrate is incorporated between the oxide and the substrate. These models explain the observed frequency dependence of the capacitance-voltage ( C - V ) characteristics of these devices. Techniques are presented for determining the impurity profile of the buried layer from the low frequency C - V measurements made on MOS transistors. The majority carrier mobilities in the buried layer and at the surface are measured for the BCCD's and compared to the surface minority carrier mobility measured for the surface channel CCD's. Generation lifetimes at the surface, in the buried layer and in the underlying substrate are determined from capacitance-time (pulse bias C - t ) measurements and leakage current measurements of the MOS capacitors and transistors. Methods are demonstrated whereby the depth from the oxide interface of the potential minimum (depth of the buried channel) and its potential can be determined as a function of the various applied biases.

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Citations
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Journal ArticleDOI

Characteristics of inversion-channel and buried-channel MOS devices in 6H-SiC

TL;DR: In this paper, gate-controlled Diodes and MOSFETs are investigated in the wide band-gap semiconductor 6H-SiC and an effective electron mobility of 20 cm/sup 2/Vs is measured for the inversion-channel devices and a bulk electron mobility is found in the channel of the buried-channel MOS-FET.
Journal ArticleDOI

Linearity of electrical charge injection into charge-coupled devices

TL;DR: In this article, the potential equilibration method was used for CCDs with any number of phases and it was shown that, if the active gate areas are suitably enlarged, harmonic distortions of less than -60 dB may be expected.
Journal ArticleDOI

Analysis and characterization of the depletion-mode IGFET

TL;DR: Using simple charge-voltage relationships, a four-terminal model is developed for the depletion-mode IGFET, where device threshold voltage, drain saturation voltage, and conditions for surface inversion are explicitly given as a function of these parameters.
ReportDOI

Reliability Prediction Modeling of New Devices.

Roger G Long, +1 more
TL;DR: Reliability prediction models for high density microcircuits including magnetic bubble and charge-coupled device memories for inclusion in MIL-HDBK-217C, 'Reliability Prediction of Electronic Equipment'.
Journal ArticleDOI

Noise measurements in charge-coupled devices

TL;DR: In this article, the authors measured the noise levels at the output of surface and bulk channel charge-coupled devices with three-phase overlapping polysilicon electrodes and showed that the intrinsic noise levels due to the extrinsic noise sources (pulser noise and electrical insertion noise) are above the expected theoretical values.
References
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Book

Physics and technology of semiconductor devices

TL;DR: The Planar Technology of Semiconductor Surfaces is described in this article, where it is shown that the planar planar technology can be used to model the surface effects on p-n junction transistors.
Journal ArticleDOI

Surface states at steam-grown silicon-silicon dioxide interfaces

TL;DR: In this article, a method of determining the energy distribution of surface states at silicon-silicon dioxide interfaces by using low-frequency differential capacitance measurements of MOS structures is described.
Journal ArticleDOI

Surface effects on p-n junctions: Characteristics of surface space-charge regions under non-equilibrium conditions

TL;DR: In this article, the surface space-charge region associated with a p-n junction is studied theoretically and experimentally, and the theory of MOS structures is extended to the case where the surface-space charge region is not in equilibrium, which is demonstrated by capacitance and conductance measurements performed on gate-controlled planar silicon diodes.
Journal ArticleDOI

Investigation of thermally oxidised silicon surfaces using metal-oxide-semiconductor structures

TL;DR: The results of a comprehensive study of the overall electrical characteristics of thermally oxidised silicon surfaces are presented, and interpreted on the basis of a simple physical model of the MOS structure as mentioned in this paper.
Journal ArticleDOI

Interpretation of surface and bulk effects using the pulsed MIS capacitor

TL;DR: In this article, the effect of surface generation on the C-t response and Zerbst plot is demonstrated and values for s0 are correlated with the density of fast surface states.
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