Patent
Method for verification of crosstalk noise in a CMOS design
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TLDR
In this article, a methodology is provided that is a practical approach to full-chip crosstalk noise verification, using either timing information or functional information, and a grouping based method is described for identification of potential victims and associated aggressors.Abstract:
In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups.read more
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References
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Journal ArticleDOI
PRIMA: passive reduced-order interconnect macromodeling algorithm
TL;DR: In this article, an algorithm for generating provably passive reduced-order N-port models for linear RLC interconnect circuits is described, in which, in addition to macromodel stability, passivity is needed to guarantee the overall circuit stability.
Journal ArticleDOI
Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs
TL;DR: In this paper, a closed-form formula for a waveform of the RC interconnection line with practical boundary conditions is derived, and the optimum linewidth that minimizes RC delay and the trend of RC delay in the scaled-down VLSIs are discussed.
Journal ArticleDOI
Crosstalk reduction for VLSI
TL;DR: An expression for the coupled noise integral and a bound for the peak coupled noise voltage are derived which shows order of magnitude improvements in both accuracy and fidelity compared to the charge sharing model used in previous work.
Proceedings ArticleDOI
Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm
Peter Feldmann,Roland W. Freund +1 more
TL;DR: A method for the efficient computation of accurate reduced-order models of large linear circuits is described, which employs a novel block Lanczos algorithm to compute matrix Padé approximations of matrix-valued network transfer functions.
Journal ArticleDOI
A simple approach to modeling cross-talk in integrated circuits
TL;DR: In this paper, a simple engineering approach for rapid simulation of cross-talk in mixed-mode IC's using SPICE is presented, which shows that while an SOI-based process provides high isolation from crosstalk at low operating frequencies, its benefit is lost at high frequencies.