Proceedings ArticleDOI
MUTARCH: Architectural diversity for FPGA device and IP security
Robert Karam,Tamzidul Hoque,Sandip Ray,Mark Tehranipoor,Swarup Bhunia +4 more
- pp 611-616
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TLDR
This paper presents a fundamentally different and novel approach to FGPA security that can protect against all major attacks on FPGA, namely, unauthorized in-field reprogramming, piracy of FPGAs intellectual property (IP) blocks, and targeted malicious modification of the bitstream.Abstract:
Field Programmable Gate Arrays (FPGAs) are being increasingly deployed in diverse applications including the emerging Internet of Things (IoT), biomedical, and automotive systems. However, security of the FPGA configuration file (i.e. bitstream), especially during in-field reconfiguration, as well as effective safeguards against unauthorized tampering and piracy during operation, are notably lacking. The current practice of bitstreram encryption is only available in high-end FPGAs, incurs unacceptably high overhead for area/energy-constrained devices, and is susceptible to side channel attacks. In this paper, we present a fundamentally different and novel approach to FPGA security that can protect against all major attacks on FPGA, namely, unauthorized in-field reprogramming, piracy of FPGA intellectual property (IP) blocks, and targeted malicious modification of the bitstream. Our approach employs the security through diversity principle to FPGA, which is often used in the software domain. We make each device architecturally different from the others using both physical (static) and logical (time-varying) configuration keys, ensuring that attackers cannot use a priori knowledge about one device to mount an attack on another. It therefore mitigates the economic motivation for attackers to reverse engineering the bitstream and IP. The approach is compatible with modern remote upgrade techniques, and requires only small modifications to existing FPGA tool flows, making it an attractive addition to the FPGA security suite. Our experimental results show that the proposed approach achieves provably high security against tampering and piracy with worst-case 14% latency overhead and 13% area overhead.read more
Citations
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Journal ArticleDOI
Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense
TL;DR: This paper investigates the potential security threats originated from the untrusted CAD tools and exploits the principle of moving target defense (MTD) to propose an FPGA-oriented MTD (FOMTD) method that achieves better resilience against Trojan inserts and consumes 50% less dynamic power.
Journal ArticleDOI
Hardware Obfuscation and Logic Locking: A Tutorial Introduction
TL;DR: The authors give a comprehensive overview of current countermeasures that can be used at RTL, gate-, and layout-level to protect your design with a focus on combinational and sequential logic locking and a discussion on merits, overheads, and shortcomings of such techniques.
Proceedings ArticleDOI
Securing FPGA-based obsolete component replacement for legacy systems
TL;DR: A Runtime Pin Grounding (RPG) scheme to ground the unused pins and check the pin status at every clock cycle to prevent the Trojans on FPGA from receiving external inputs or leaking sensitive information, and a hardware MTD method to reduce the hardware Trojan bypass rate.
Journal ArticleDOI
Hidden in Plaintext: An Obfuscation-based Countermeasure against FPGA Bitstream Tampering Attacks
Tamzidul Hoque,Kai Yang,Robert Karam,Shahin Tajik,Domenic Forte,Mark Tehranipoor,Swarup Bhunia +6 more
TL;DR: A novel obfuscation-based approach to achieve strong resistance against both random and targeted pre-configuration tampering of critical functions in an FPGA design and a redundancy-based technique is proposed to thwart targeted, rule-based, and random tampering.
Journal ArticleDOI
New Light Weight Threshold Voltage Defined Camouflaged Gates for Trustworthy Designs
TL;DR: New light weight TVD static and dynamic logic (TVD-SL and TVD-DL) based camouflaged gates are proposed that are best suited for the development of secure and portable devices for the Internet of Things applications.
References
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Proceedings ArticleDOI
EPIC: ending piracy of integrated circuits
TL;DR: A novel comprehensive technique to end piracy of integrated circuits (EPIC), which requires that every chip be activated with an external key, which can only be generated by the holder of IP rights, and cannot be duplicated.
BookDOI
Introduction to Hardware Security and Trust
Mohammad Tehranipoor,Cliff Wang +1 more
TL;DR: This book provides the foundations for understanding hardware security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.
Journal ArticleDOI
VTR 7.0: Next Generation Architecture and CAD System for FPGAs
Jason Luu,Jeffrey Goeders,Michael Wainberg,Andrew Somerville,Thien Yu,Konstantin Nasartschuk,Miad Nasr,Sen Wang,Tim X. Liu,Nooruddin Ahmed,Kenneth B. Kent,Jason H. Anderson,Jonathan Rose,Vaughn Betz +13 more
TL;DR: Recent advances in the open source Verilog-to-Routing (VTR) CAD flow are described that enable further research in these areas and release new FPGA architecture files and models that are much closer to modern commercial architectures, enabling more realistic experiments.
Journal Article
PUFKY: A Fully Functional PUF-based Cryptographic Key Generator
TL;DR: In this paper, the authors present PUFKY, a practical and modular design for a cryptographic key generator based on a Physically Unclonable Function (PUF), which uses a highly optimized ring oscillator PUF (ROPUF) design.
Proceedings ArticleDOI
On the vulnerability of FPGA bitstream encryption against power analysis attacks: extracting keys from xilinx Virtex-II FPGAs
TL;DR: A successful attack on the bitstream encryption engine integrated in the widespread Virtex-II Pro FPGAs from Xilinx, using side-channel analysis, is developed, believed to be the first attack against thebitstream encryption of a commercial FPGA reported in the open literature.
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